View AT73C203-EK1_1424104.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2742b?pmgmt?03/04 features dc to dc step down 1.2 a, 0.9v (dynamically adjustable to 0.87v/1.1v/1.2v) dc to dc step down 1.2 a, 1.2v (dynamically adjustable to 1.0v/1.1v/1.3v) or 1.75v (dynamically adjustable 1.65v/1.70v/1.80v) dc to dc step down 1.2 a, 1.8v (dynamically adjustable to 1.70v/1.75v/1.85v) or 2.5v (dynamically adjustable 2.3v/2.4v/2.6v) dc to dc step up/down 520 ma, 3.3v (dynamically adjustable to 3.0v/3.1v/3.4v) dual battery chargers: li+ precharge, fast charge, top-up charge, 4.1v (or adjustable), processor tuned algorithms ? usb trickle charge: precharge flat battery from usb pre-enumeration, then auto- wake of processor at 3.8v battery level ? battery charge select: 25 ma to 500 ma ? real-time charge inhibit: allows charge suspend (e.g. during tx slots) supply monitor of four power sources: thermistors, temperature, dc/dc rails, all supplied with out-of-regulation threshold detection sim interface: sim / usim, 1.8v / 3.0v standards, integrated tx and rx data fifo spi control interface: up to 13 mhz; tuned for sa1110/pxa250/pxa255 1.2 mhz spi, 128 8-bit registers power on reset: for sa1110/pxa250/pxa255 architectures plus additional sequenced system level resets voltage and temperature supervision calibrated voltage reference 8-bit adc with 5-input multiplexer integrated oscillator, start-up and self-protection circuitry off power: 60 a with external ?button select? for restart applications include: pdas, pcmcia cards, smart phones, pocket pcs, 3g applications, intel ? xscale? powered applications description the at73c203 device provides an integrated solution to portable and handheld appli- cations built around microprocessors requiring ?smart? power management functions, such as pdas, palmtop computers, point-of-sales terminals, 3g modems, etc. its compact package outline and small size of external components make the at73c203 suitable for pcmcia card power management as well. the at73c203 integrates a power switch controller that, when connected to an exter- nal power switch, may be used for automatically selecting one of four possible power sources: internal battery external battery plugtop power supply unit 5v (psu) pc host usb supply the power switch output (vdd-psu line) is connected directly to external auxiliary components such as a radio or any other ?current hungry? module. the at73c203 is also equipped with four digital rails from vdd-psu to supply a base- band chip, a reset generator for the baseband chip, and a spi interface to control the at73c203 via an internal register set. the usim interface allows the application pro- cessor to communicate with and control a usim card. charge control enables the application processor to charge the battery from the psu or usb. a state machine can also determine whether to charge the internal battery through usb at start-up. additionally, hardware monitoring gives information to the application processor when a voltage drop occurs (programmed via internal registers). power management at73c203 power management ic for datacom platforms
2 at73c203 2742b?pmgmt?03/04 functional diagram figure 1. at73c203 functional diagram stand alone ldo regulator digital control serial interface 8-bit adc measurement bridge temperature sensor battery charger power switch internal 900 khz oscillator very low temperature shift clock distributor power management state machine iso 7816 uart internal voltage reference sim level shifter sim ldo 1.8 v/2.8 v/10 ma dc-dc converter boost - ldo 3.3v (3 v to 5.4 v)/520 ma dc-dc converter buck 1.8 v (1.7 v to 2.6 v)/1.2 a dc-dc converter buck 1.2 v (1 v to 1.8 v)/1.2 a dc-dc converter buck 0.9 v (0.87 v to 1.2 v)/1.2 a
3 at73c203 2742b?pmgmt?03/04 pin description table 1. at73c203 pin description signal name pin type pack pin level esd protection comments avss a-i a1 avss esd ground seldc175 d-i b2 gnddig - vsauv avss - vswin digital control seldc25 d-i b1 gnddig - vsauv avss - vswin digital control nen_rail3 d-i/o a3 gnddig - vsauv avss - vswin digital control nen_rail4 d-i/o a2 gnddig - vsauv avss - vswin digital control nasic_reset d-o c3 gnddig - vout3 avss - vout3 reset nboard_reset d-o c1 gnddig - vout3 avss - vout3 reset board_reset d-o c2 gnddig - vout3 avss - vout3 reset nproc_reset d-o d4 gnddig - vout3 avss - vout3 reset nproc_reset_out d-i d3 gnddig - vout3 avss - vout3 reset nasic_reset_request d-i d1 gnddig - vout3 avss - vout3 reset power_en d-i d2 gnddig - vout3 avss - vout3 digital control syst_clk d-i a4 gnddig - vout3 avss - vout3 digital control nusim_int d-o e1 gnddig - vout3 avss - vout3 digital control nint d-o e2 gnddig - vout3 avss - vout3 digital control button_out d-o e3 gnddig - vout3 avss - vout3 digital control chg_inhibit d-i f1 gnddig - vout3 avss - vout3 digital control test1 d-i/o f2 gnddig - vsauv avss ? vsauv test test2 d-i/o f3 gnddig - vsauv avss - vsauv test idbits3 d-i/o g1 gnddig - vout3 avss - vout3 digital control idbits2 d-i/o f4 gnddig - vout3 avss - vout3 digital control idbits1 d-i/o g2 gnddig - vout3 avss - vout3 digital control idbits0 d-i/o h1 gnddig - vout3 avss - vout3 digital control sdo d-i/o g3 gnddig - vout3 avss - vout3 spi sdi d-i h2 gnddig - vout3 avss - vout3 spi sclk d-i j1 gnddig - vout3 avss - vout3 spi nsen d-i e5 gnddig - vout3 avss - vout3 spi gnddig a-i k1 gnd avss - gnddig digital ground vout3 a-i k2 gnddc3 - vout3 avss - vboost dcdc rail3 vboost a-i j2 gnddc3 - vddpsu pcboost dcdc rail3 dh3 a-o k3 gnddc3 - vddpsu avss - vboost dcdc rail3 gnddc3 a-i h3 gnd avss - gnddc3 dcdc rail3 dl3 a-o j3 gnddc3 - vddpsu avss - pcmax dcdc rail3 vddpsu3 a-i g4 gnddc3 - vddpsu avss - pcmax dcdc rail3
4 at73c203 2742b?pmgmt?03/04 dcsense3 a-i h4 gnddc3 - vddpsu avss - pcmax dcdc rail3 vout2 a-i k4 gnddc2 - vout2 avss - pcmax dcdc rail2 dcsense2 a-i h5 gnddc2 - vddpsu avss - pcmax dcdc rail2 dh2 a-o k5 gnddc2 - vddpsu avss - pcmax dcdc rail2 vddpsu2 a-i g5 gnddc2 - vddpsu avss - pcmax dcdc rail2 gnddc2 a-i j4 gnd avss - gnddc2 dcdc rail2 dl2 a-o j5 gnddc2 - vddpsu avss - pcmax dcdc rail2 vout1 a-i k6 gnddc1 - vout1 avss - pcmax dcdc rail1 dcsense1 a-i h6 gnddc1 - vddpsu avss - pcmax dcdc rail1 dh1 a-o k7 gnddc1 - vddpsu avss - pcmax dcdc rail1 vddpsu1 a-i g6 gnddc1 - vddpsu avss - pcmax dcdc rail1 gnddc1 a-i j6 gnd avss - gnddc1 dcdc rail1 dl1 a-o j7 gnddc1 - vddpsu avss - pcmax dcdc rail1 vout4 a-i j10 gnddc4 - vout4 avss - pcmax dcdc rail4 dcsense4 a-i k9 gnddc4 - vddpsu avss - pcmax dcdc rail4 dh4 a-o k8 gnddc4 - vddpsu avss - pcmax dcdc rail4 vddpsu4 a-i k10 gnddc4 - vddpsu avss - pcmax dcdc rail4 gnddc4 a-i j9 gnd avss - gnddc4 dcdc rail4 dl4 a-o j8 gnddc4 - vddpsu avss - pcmax dcdc rail4 sim_clk d-o h10 gnddig - vsim avss - pcmax sim sim_reset d-o h9 gnddig - vsim avss - pcmax sim sim_io d-i/o g7 gnddig - vsim avss - pcmax sim sim_vcc a-o g8 gnddig - vsim avss - pcmax sim regulator gnd_ch a-i e6 gnd avss - gndch charger bat2_ch a-i f7 gndch - maxsupply avss - pcmax charger bat1_ch a-i f10 gndch - maxsupply avss - pcmax charger bat2_ch_on a-o f9 gndch - maxsupply avss - pcmax charger bat1_ch_on a-o f8 gndch - maxsupply avss - pcmax charger batsensem a-i e10 gndch - maxsupply avss - pcmax charger batsensep a-i e9 gndch - maxsupply avss - pcmax charger usb_ch_en a-o e8 gndch - maxsupply avss - pcmax charger usb_ch a-i d10 gndch - maxsupply avss - pcmax charger gabat1 d-o e7 gnda1 - maxsupply avss - pcmax power switch gabat2 d-o d9 gnda1 - maxsupply avss - pcmax power switch gapsu d-o c10 gnda1 - maxsupply avss - pcmax power switch vddpsu a-i g10 gnda1 - vddpsu avss - pcmax power switch table 1. at73c203 pin description (continued) signal name pin type pack pin level esd protection comments
5 at73c203 2742b?pmgmt?03/04 bat1_pio a-i d8 gnda1 - bat1 avss - pcmax power switch bat2_pio a-i c9 gnda1 - bat2 avss - pcmax power switch psu_pio a-i b10 gnda1 - psu avss - pcmax power switch usb_pio a-i d6 gnda1 - usb avss - pcmax power switch maxsupply a-o a10 gnda1 - maxsupply pcmax power switch gnd_pio a-i b9 gnd avss - gnda1 power switch vreffuse a-i a9 avss - 5.5v avss-vswin fuses vbias a-o c8 gnda - vsauv avss - vswin reference generator cref a-o a8 gnda - vsauv avss - vswin reference generator vmes a-o b8 gnda - vsauv avss - vswin measurement bridge portest d-o d7 gnda - vsauv avss - vswin power on reset therm1 a-o c7 gnda - vsauv avss - vswin current generator therm2 a-o a7 gnda - vsauv avss - vswin current generator gnda a-i b7 gnd avss - gnda internal regulator vsauv a-o c6 gnda - vsauv avss - vswin internal regulator vsw a-i a6 gnda - vswin avss - vswin internal regulator vswin a-i b6 gnda - vswin pcvswin internal regulator scan_test_md d-i/o c4 gnddig - vsauv avss - vswin test scan_enable d-i/o a5 gnddig - vsauv avss - vswin test nshutdown d-i b5 gnddig - vsauv avss - vswin digital control pcmcia d-i c5 gnddig - vsauv avss - vswin digital control sim_pres d-i g9 gnddig - vsauv avss - vswin digital control button_in d-i d5 gnddig - vsauv avss - vswin digital control nc b4 not connected nc e4 not connected nc h8 not connected nc h7 not connected nc f5 not connected nc b3 not connected nc f6 not connected table 1. at73c203 pin description (continued) signal name pin type pack pin level esd protection comments
6 at73c203 2742b?pmgmt?03/04 application schematic figure 2. at73c203 application schematic digital control 8-bit adc measurement bridge temperature sensor battery charger power switch internal 900 khz oscillator clock distributor internal voltage reference generator sim ldo 1.8v 30 ma 2.8v 50 ma dc-dc converter 3.3v (3 v to 5.4 v)/520 ma dc-dc converter 1.8 v (1.7 v to 2.6 v)/1.2 a dc-dc converter 1.2 v (1 v to 1.8 v)/1.2 a dc-dc converter buck 0.9 v (0.87 v to 1.2 v)/1.2 a bat1_pio usb gabat1 gabat2 gapsu usb_ch usb_ch_en batsensep batsensem bat1_ch_on bat1_ch bat2_ch_on bat2_ch cref sim-v cc dh3 dl3 dcsense3 dh2 dl2 dcsense2 dh1 dl1 dcsense1 dh4 dl4 dcsense4 bat2_pio psu_pio ldo 3.3v internal regulator 2.5v 5 ma current generator 2v power 0n reset internal 10 khz oscillator psu driver driver digital sim c21 vmes vddpsu maxsupply usb_pio vddpsu4 vout4 c16 c17 c18 c19 c20 c22 t1 t2 t3 vddpsu1 vddpsu2 vddpsu3 vout1 vout2 vboost vout3 c1 c2 c3 c4 c7 c8 c5 c6 c9 r1 t4 l1 r2 l2 t5 r3 l3 t6 t7 d1 r4 l4 t8 therm1 therm2 vbias vsauv vsw vswin c13 c10 c11 c12 r5 psu usb bat1 bat2 d2 d3 d4 d5 r6 c15 c14 t10 t9 syst_clock nusim_int sim_pres sim_reset sim_io sim_clk nen_rail4 nen_rail3 sdo sdi nsen sclk nshutdown seldc175 seldc25 button_in button_out nint power_en nproc_reset_out nproc_reset board_reset nasic_reset nasic_reset_request chg_inhibit id_bits0 id_bits1 id_bits2 id_bits3 pcmcia nboard_reset
7 at73c203 2742b?pmgmt?03/04 architecture overview figure 3. at73c203 architecture overview system level description several power sources may be used to power the at73c203 circuitry including an inter- nal or external battery, external psu or usb. the internal battery is always physically present in the unit, but any or all of the other sources may be connected or disconnected at any time. the at73c203 enables one application to be powered up from the correct source of up to four possible power sources under hardware control. when powered, the external processor can monitor the input power sources and initiate battery charging as required via the spi. the application processor is also able to enable/disable the circuit power rails and configure a low power sleep state. an input-multiplexed 8-bit adc is available that allows the application processor to mon- itor the presence of and measure the voltage of the power sources, batteries and rails. an associated threshold and comparator circuit may be used to indicate to the proces- sor that an out-of limit event has occurred. the battery charging circuitry is designed to allow charging from the psu input and to allow current-limited 'supplement' charging from the usb input. in both cases, the chargers operate under processor control and monitoring with hardware safety lockout. when the psu is present, a power path is selected (e.g. from a dc jack) through the power switching circuitry to the external components (e.g. radio and companion chips or chipset, baseband chip etc.) this power path enables the application processor to boot up. a parallel path exists from the psu input (e.g. jack) through current limiting devices to two battery chargers. the current switches only block reverse current when disabled so care must be taken when controlling them. when a usb input is powered, a single power path exists through the current limiting devices to the two battery chargers. the hardware defaults to a current limit of 100 ma digital supply rails spi sim powerswitch controller charger controller monitoring digital i/o bat 1 bat 2 psu usb radio vout1 vout2 vout3 vout4 li+ 1600 mah li+ ac/dc pc host usb plug top 800 mah companion chip or chipset, eg: application processor, baseband soc core and digital powerswitch vdd-psu
8 at73c203 2742b?pmgmt?03/04 but the application processor may set 500 ma after negotiation with the pc. this power should always be used to charge the batteries in the absence of the psu power source. sim/usim interface hardware is provided, allowing the application processor to commu- nicate and control a sim/usim card according to the required analog and digital specifications. most of the blocks are switched on or off by the digital control block (not all the control lines are drawn on the block diagram). only the supply monitor, digital control, power on reset, 10 khz internal oscillator and internal regulator are always on. all these blocks are designed to have very low power consumption, capable of achiev- ing three months standby time for the application. functional integration the at73c203 integrates the following functions: supply monitor the supply monitor block enables the at73c203 to correctly switch the four main sup- plies (two batteries, psu and usb). all the outputs are sent to the digital control. internal regulator the internal regulator is a low drop out regulator generating v sauv at 2.5v with a maxi- mum load of 5 ma. its input is v sw . power-on reset the internal power-on reset is supplied by v sauv and resets the at73c203 digital cir- cuitry at 2v. 10 khz internal oscillator the 10 khz low power oscillator is the clock source for the at73c203 digital circuitry. v sauv supplies it. digital control the digital block controls each block and drives the spi interface and the different inter- rupts (external and internal). the controls, inputs and outputs are level shifted when necessary and protected to avoid current flowing between the blocks (not represented in the block diagram). a state machine controls the at73c203 circuitry according the sup- plies and inputs states. a table of registers is accessible via spi to command or read status of the at73c203. reference generator the reference generator provides the at73c203 with a precise bandgap voltage (v ref ) and current bias (i ref ) used by all analog blocks (dc/dc, adc, charger) except the core blocks. it is turned off under digital control when necessary and is v sauv supplied. 900 khz oscillator and clock distribution the 900 khz oscillator provides the clock to all dc/dc converters. the clock distributor provides phased clocks to the dc/dc converters to avoid switching at the same time. the frequency of the oscillator is trimmed during production to optimize the dc/dc efficiency. dc to dc step down 1.2 a, 0.9v the dc to dc step down 1.2a, 0.9v (dynamically adjustable to 0.87v/0.9v/1.1v/ 1.2v) is a programmable buck dc/dc converter dedicated to advanced sub-micron pro- cessors and soc asic logic cores requiring dynamic power management at low voltages and high currents. the default voltage is 0.9v for which the device is optimized. the external components needed include a current sensing resistor, a dual pmos- nmos, an inductor and an output capacitor.
9 at73c203 2742b?pmgmt?03/04 the application processor can change the output voltage via registers accessible by spi. when the cell is off, the output is in high impedance state. if not used, this section can be permanently deactivated. dc to dc step down 1.2a, 1.2v or 1.75v the dc to dc step down 1.2a, 1.2v (dynamically adjustable to 1.0v/1.1v/1.2v/1.3v) is a programmable buck synchronous dc/dc converter dedicated to the application pro- cessor core and/or a ?companion? asic soc processor core. the default voltage is 1.2v. an external pin can select 1.75v output voltage with tuning: 1.80v, 1.70v or 1.65v. the entire cell is optimized for 1.2v. the application processor can change the output voltage as described above via registers accessible by spi. the external components needed include a current sensing resistor, a dual pmos- nmos, one inductor and one output capacitor. when the cell is off, the output is pulled to ground. if not used, this section can be permanently deactivated dc to dc step down 1.2a, 1.8v or 2.5v the dc to dc step down 1.2a, 1.8v (dynamically adjustable to 1.70v/1.75v/1.80v/1.85v) is a programmable buck synchronous dc/dc converter ded- icated to the supply of recent and future flash and sdram memories and their associated buses on the application processor i/o section as well as additional memory extension modules such as cf cards, mmcards, memory stick, etc. the default voltage is 1.8v. an external pin can select 2.5v output voltage with tuning: 2.6v, 2.4v and 2.3v. the entire cell is optimized for 1.8v. the application processor can change the output voltage as described above via registers accessible by spi. the external components needed include a current sensing resistor, a dual pmos- nmos, an inductor and an output capacitor. a low quiescent current mode is implemented when a very low standby current is needed with a parallel voltage regulator. when the cell is off, the output is in high impedance state. dc to dc step up/ down 520 ma, 3.3v the dc to dc step up/down 520 ma, 3.3v (dynamically adjustable to 3.0v/3.1v/ 3.4v) is a boost dc/dc 3.6v converter followed by a linear drop out regulator. it is intended to supply 3.3v i/os needed in the application (audio codec, lcd, memories). the external components needed include a current sensing resistor, an nmos, a schottky diode, an inductor and an output capacitor. the default value of the ldo is 3.3v but three other values can be programmed: 3.1v, 3.2v and 3.4v. the entire cell is optimized for 3.3v. the application processor can change the output voltage as described above via registers accessible by spi. when the cell is off, the output is pulled to ground. power switch controller the power switch controller drives an external pmos switch to multiplex vdd-psu from the internal or external battery or usb. the purpose of this cell is to guarantee a suffi- cient supply for vdd-psu and to limit voltage drops even during switchover. in-rush current and current flow between the inputs must be avoided. when this cell is off, vdd-psu is left in high impedance. current generators two accurate current generators allow the measurement of the resistance of two exter- nal battery thermistors. the outputs v the1 and v the2 go to the measurement bridge. the
10 at73c203 2742b?pmgmt?03/04 current generators are supplied by v sauv and controlled by the digital control for use during battery charging. temperature sensor the temperature sensor voltage output depends linearly on temperature. it is supplied by v sauv and driven by the digital control. the temperature seen by the sensor is directly related to the chip activity and the power internally dissipated. to get a good indication of the ambient temperature, the software must take into account this offset. measurement bridge/ multiplexer the measurement bridge provides adapted voltages of the internal and external batter- ies, dc/dc converter outputs, usb, vdd-psu, v the1 and v the2 to the multiplexed input of the serial analog to digital converter. analog to digital converter an 8-bit analog to digital converter is inte grated into the at73c203 to give information about voltage and temperature to the application processor via the spi interface. li-ion/battery chargers the battery chargers both have stand-alone constant current (cc) precharge and micro- processor-controlled cc fast charge as well as top-off mode end-of-charge algorithm. the digital block controls this cell. all current and voltage settings are programmable via registers. the charger controller is divided into two si milar parts, one for the internal battery and one for the external battery. each charger multiplexes the source (usb or psu) and lim- its the programmable current charge (via sense resistor). an external pmos and a schottky diode are needed for each charger. the application processor must check that the temperature allows charging via the cur- rent generator, measurement bridge and adc. usim voltage regulator a regulator is provided to power up the usim card. it is supplied directly from vdd_psu. one of two different voltages can be selected: 2.8v (50 ma) 1.8v (30 ma) by default, the regulator is in power-down mode. the pins connected to the usim (sim_clk, sim_io, sim_pwr) must have driver specification according to ets ts 102 221. usim digital section the main part of the usim digital section is an iso7816 uart compatible interface. reset generation a reset is generated via the internal state machine. the timer for this internal reset gen- erator is 150 ms (typical). the application processor can set the at73c203 to off mode via the power_en pin. the ?internal? reset is active at low level. another way to generate a reset is to program it through the monitoring function (adc with measurement bridge and data registers). the ?monitoring? reset is active at low level. a logical and of the ?internal? and the ?monitoring? reset drives the reset of the external application processor (nproc_reset pin). other pins are used to generate separated resets for external ?companion? chips such as baseband chips. nshutdown forces the at73c203 internal digital block to the reset state. this turns all the supplies off and then restarts the internal state machine.
11 at73c203 2742b?pmgmt?03/04 recommended external components absolute maximum ratings table 2. recommended external components schematic reference component reference c1, c3, c5, c8, c16, c17, c18, c19 22 f ceramic c2, c4, c6, c7, c9 47 f tantalum low esr tpsw476m010r0150 or equivalent c10, c20 100 nf xr5 10% c11, c13, c22 2.2 f x5r 10% c12 330 nf x5r 10% c14, c15 10 nf x5r 10% c21 100 pf x5r 10% l1, l4 4.7h smt3106-471m (gowanda ? ) or equivalent l2, l3 10 h smt3106-102m (gowanda) or equivalent d2, d3 bat54c d4, d5, d1 mbra120lt3 (on semiconductor ? ) or equivalent r1, r2, r4 100 m ? 2% 250mw r3 100 m ? 2% 250mw r5 220 k ? 1% r6 200 m ? 2% 50mw t1, t2, t3 si4965dy t4, t5, t8 si5513dc t6 si1400dl t7, t9, t10 si8401dl t11 si1405dl operating ambient temperature........................-40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature......................................-55c to + 150c bat1_pio, bat2_pio, psu_pio, usb_pio, usb_ch, bat1_ch, bat2_ch, vsw_in to ground pins.....................................................-0.3v to +6.5v
12 at73c203 2742b?pmgmt?03/04 recommended operating conditions table 3. recommended operating conditions parameter conditions min max unit operating ambient temperature -40 +85 c storage temperature -55 +150 c signal to ground pins bat1_pio, bat2_pio, psu_pio, usb_pio, usb_ch, bat1_ch, bat2_ch, vsw_in -0.3 +5.5 v
13 at73c203 2742b?pmgmt?03/04 system overview startup and off mode most of the blocks are switched on or off by the digital block. only the supply monitor, digital control, power-on reset, internal 10khz oscillator and internal regulator are always on. figure 4. start-up overview the system has two modes: off and active. off mode: all the cells are off except the supply monitor, digital control, power-on reset, internal 10 khz oscillator and internal regulator. these blocks are designed to consume very little power in order to achieve an off time of three months from a 600 ma fully charged battery. active mode: the power switch and all the dc/dc controllers are on. all the other cells are controlled by software (via internal registers). internal oscillator 10 khz power-on reset 2 v internal regulator 2.5 v 5 ma supply monitor digital control por1 por2 rint bat1_sm bat2_sm psu_sm usb_sm v sw_in v sw v sauv bat1 bat2 psu usb d3 d2 c12 c11
14 at73c203 2742b?pmgmt?03/04 startup description v sw_in is an analog or of bat1, bat2, usb and psu implemented using four external schottky diodes. schottky diod es are used to minimize the power source to the at73c203 voltage drop in order to maximize battery life. see figure 4 on page 13. when at least one of these supplies are present, v sw_in tracks the highest voltage of the four inputs. an internal resistor (rint) between v sw and v sw_in limits the current flowing through the diodes and c12. v sw is the input of the internal regulator, which delivers the supply for the digital, oscilla- tors, power-on reset, measurement bridge, reference generator, ad converter, temperature sensor, current generator and supply monitor blocks. only a small current is supplied from v sw_in which minimizes the voltage drop across the schottky diodes. power-on-reset protection figure 5 below and figure 6 on page 15 illustrate the start-up sequence of the at73c203 under the following conditions. one supply is present (psu), the others are connected to ground or not present. por1 supervises v sw . it goes to low level after the start-up time of the internal regulator. por2 supervises v sauv . it goes to low after v sauv reaches the correct value for the digital core to run. both v sw and v sauv must be stable for the digital block to operate correctly. the reset for the digital core is the logical or of por1 and por2. figure 5. psu rising sequence note: 1. t startupreg = startup time of the internal regulator. t startupreg psu v sw v sauv por1 por2 (1)
15 at73c203 2742b?pmgmt?03/04 figure 6. psu drop sequence note: 1. t shutdownreg = shutdown time of the internal regulator. state machine description state machines for the start-up and off modes are described in the following pages. the state machine is completely synchronous to the internal 10 khz oscillator and all the signals connected to the analog blocks are level shifted as necessary and protected to allow a reliable level. usb_fst is a digital flag. by default usb_fst is set at 0. if the digital core begins to precharge battery 1 from usb at startup, usb_fst is set to 1 by the internal digital block. the application processor can reset it to 0 via the spi if needed by setting the usb_fcr flag. this flag acts to avoid digital oscillation when the charge through usb is the start condition. it is also used to inform the application processor that the at73c203 has charged the internal battery from usb with a minimal amount of charge. the digital core can also put the at73c203 via usb_scr register into a mode where the digital core is off and battery1 is charged (25 ma) through usb up to 4.1v. in this mode (see figure 10 on page 19) and when battery1 is precharged by usb (see figure 8 on page 17), a ctn thermistor must be connected to therm1. the ctn thermistor used must be equivalent to the thermistor 103jt-025 from semitec ? . temperature to allow precharging through usb: 0c to 60c. safety timer for the usb stand alone mode: 1 hour safety timer for the usb sleep mode: 24 hours psu v sw v sauv por1 por2 t shutdownreg (1)
16 at73c203 2742b?pmgmt?03/04 figure 7. startup state machine (1of 3) dcdc_3v3_start dcdc_3v3_on pow_sw_start pow_sw_on bgp-osc_start start charger_debounce charger_debounce guard_time_end guard_time init 2 3 usb_debounce after power-on reset flag_usb = 0 wait 1 ms psu present button not pressed psu not present end of debouncing timer (10 ms) end of debouncing timer (10 ms) end of bandgap and dc/dc timer end of power switch timer psu not present (vbat1 or vbat2) present and not flat button pressed 1 1 2 1 first counter running (wait stabilization of the internal clock) psu unplugged usb plugged in flag_usb = 0 button not pressed 10 ms timer for debouncing running 2 wait psu present during 10 ms 1 wait bandgap and osc 500 k start (5 ms) 1 wait power switch start (5 ms) wait button pressed during 10 ms 3 3 3 1 2 2 startup state machine (1) usb not present
17 at73c203 2742b?pmgmt?03/04 figure 8. startup state machine (2 of 3) startup state machine (2) usb_debounce start_usb bgp_adc_start temperature_nok charger_on bat1_check battery_error temperatrue_test start 2 3 1 wait usb present during 10 ms wait temperature ok temperature correct usb unplugged bat1 < 3.8 v psu present psu present psu present end of charger timer and bat1 > 3.8v temperature correct 1 1 1 4 2 2 2 3 3 4 4 guard_time_end usb not present 2 1 wait bandgap start 5 ms 2 3 temperature not correct end of bandgap timer charger debounce guard_time_end guard_time_end guard_time_end main bandgap on current generator on adc on charger on: battery 150 ma charger timer launched 1 wait bat1 > 3.8 v during 10 ms bat1 > 3.8 v and timer still running bat1 > 3.8 v during 10 ms charger_debounce psu present usb unplugged usb deconnected or psu connected charger off psu unplugged usb plugged in flag_usb = 0 button not pressed usb_fst = 1
18 at73c203 2742b?pmgmt?03/04 figure 9. startup state machine (3 of 3) wait dc/dc converter start (5 ms) dc/dc_3v3_start 1 2 startup state machine (3) rail3_start rail1_on rail1_start rail2_on rail2_start rail4_on rail4_start reset_timer end_of_reset 2 2 1 2 2 rail1 on reset pin active rail2 on reset pin active wait dc/dc converter start (5 ms) 1 end of 3.3 v dc/dc startup and pwr_en = 1 end of dc/dc startup wait dc/dc converter start (5 ms) end of dc/dc startup rail4 on reset pin active 1 wait dc/dc converter start (5 ms) end of dc/dc startup end of reset timer reset timer launched reset pin active 1 wait end of reset timer reset pin disactivated => under software control
19 at73c203 2742b?pmgmt?03/04 figure 10. usb sleep state machine usb sleep state machine end_of_reset state rail4_off1 temperature_nok2 charger_on2 bat1_check2 battery_error2 temperatrue_test2 wait temperature ok temperature correct usb unplugged psu present psu present psu present end of charger timer and bat1 > 4.1 v temperature correct 1 1 1 4 2 2 3 4 2 3 temperature not correct usb_scr = 1 charger debounce guard_time_end guard_time_end guard_time_end rail4 off reset active charger on: battery 150 ma charger timer launched bat1 > 4.1 v and timer still running charger_debounce active after "end_of_ reset" state rail2_off1 rail2 off reset active rail1_off1 rail1 off reset active rail3_off1 rail3 off reset active psu present usb unplugged usb disconnected or psu connected
20 at73c203 2742b?pmgmt?03/04 figure 11. stop off state machine stop off state machine pwren_debounce rail4_off1 case_analysis off_mode_psu off_mode_no_psu button_release 1 2 2 guard_time_end rail4 off reset active psu present button pressed active after "end_of_ reset" state rail2_off1 rail2 off reset active rail1_off1 rail1 off reset active rail3_off1 rail3 off reset active 1 2 wait pwren = 0 during 10 ms all cells (except the core cell) are off psu not present button released during 200 ms psu not present button_debounce 1 1 wait button released 1 wait button released during 200 ms
21 at73c203 2742b?pmgmt?03/04 reset generation a reset is generated via the internal state machine as described in figure 7 on page 16, figure 8 on page 17, figure 9 on page 18 and figure 11 on page 20. the timer for the internal reset generator is 150 ms (typical). the application processor can set the at73c203 to off mode via the power_en pin (figure 11 on page 20). this ?internal? reset is active at low level. another way to generate a reset is to program it through the monitoring function. the ?monitoring? reset is active at low level. an logical and of the ?internal? reset and the ?monitoring? reset drives the reset of the external microprocessor. it is connected to the nproc_reset pin and directly drives the external microprocessor. additional pins are used to generate separated resets for the baseband chips (see fig- ure 12 below). nshutdown forces the at73c203 internal digital block to the reset state. this turns all the supplies off and then restarts the internal state machine. power-on reset resets the internal state machine. nproc_reset resets all other digi- tal parts, with the exception of the usim interface which is reset via the nboard_res pin. figure 12. reset generation architecture internal reset monitoring reset power_en nproc_reset nproc_reset_out board_res nboard_res nasic_reset nasic_reset_request nshutdown internal reset generator monitoring reset generator
22 at73c203 2742b?pmgmt?03/04 at73c203 user interface table 4. at73c203 user interface address register name access reset state general-purpose registers 0x48 gp_ident chip identification read-only 0xa0 0x4b gp_gpio_read gpio status read-only - 0x4a gp_gpio_write gpio control read/write 0x00 0x49 dc_trim digital rails trimming read/write 0x00 0x4c pws_cr power switch control read/write 0x00 0x4d pws_sr power switch status read-only - 0x4f usb_fst usb flag status read-only - 0x4e usb_fcr usb flag control write-only - usim interface registers 0x32 sim_csr usim channel status read-only - 0x34 sim_bsr usim buffer status read-only 0x00 0x36 sim_msr usim miscellaneous status read-only - 0x37 sim_imr1 usim interrupt mask 1 read/write 0x00 0x39 sim_imr2 usim interrupt mask 2 read/write 0x00 0x35 sim_mr usim mode read/write 0x80 0x33 sim_cr usim control write-only - 0x3f sim_ar usim activation read/write 0x00 0x38 sim_rhr usim receiver holding read-only - 0x31 sim_thr usim transmitter holding write-only - 0x3a sim_bdr usim baud divisor read/write 0x0c 0x3e sim_cdr usim clock divisor read/write 0x00 0x3b - 0x3c sim_rtor usim receiver time-out read/write 0x00 0x3d sim_ttgr usim transmitter time guard read/write 0x00 0x30 sim_ner usim number of errors read-only 0x00 voltage and temperature monitoring registers 0x29 mon_cr monitoring control read/write 0x00 0x00 mon_vbat1_meas monitoring vbat1 measure read-only 0x00 0x01 mon_vbat2_meas monitoring vbat2 measure read-only 0x00 0x02 mon_usb_meas monitoring usb measure read-only 0x00 0x03 mon_vddpsu_meas monitoring vddpsu measure read-only 0x00 0x04 mon_vout1_meas monitoring vout1 measure read-only 0x00 0x05 mon_vout2_meas monitoring vout2 measure read-only 0x00 0x06 mon_vout3_meas monitoring vout3 measure read-only 0x00
23 at73c203 2742b?pmgmt?03/04 0x07 mon_vout4_meas monitoring vout4 measure read-only 0x00 0x08 mon_vte1_meas monitoring vte1 measure read-only 0x00 0x09 mon_vte2_meas monitoring vte2 measure read-only 0x00 0x0a mon_vts_meas monitoring vts measure read-only 0x00 0x16 mon_vbat1_undl monitoring vbat1 under limit read/write 0x00 0x0b mon_vbat1_ovl monitoring vbat1 over limit read/write 0x00 0x17 mon_vbat2_undl monitoring vbat2 under limit read/write 0x00 0x0c mon_vbat2_ovl monitoring vbat2 over limit read/write 0x00 0x18 mon_usb_ undl monitoring usb under limit read/write 0x00 0x0d mon_usb_ovl monitoring usb over limit read/write 0x00 0x19 mon_vddpsu_ undl monitoring vddpsu under limit read/write 0x00 0x0e mon_vddpsu_ovl monitoring vddpsu over limit read/write 0x00 0x1a mon_vout1_undl monitoring vout1 under limit read/write 0x00 0x0f mon_vout1_ovl monitoring vout1 over limit read/write 0x00 0x1b mon_vout2_undl monitoring vout2 under limit read/write 0x00 0x10 mon_vout2_ovl monitoring vout2 over limit read/write 0x00 0x1c mon_vout3_undl monitoring vout3 under limit read/write 0x00 0x11 mon_vout3_ovl monitoring vout3 over limit read/write 0x00 0x1d mon_vout4_undl monitoring vout4 under limit read/write 0x00 0x12 mon_vout4_ovl monitoring vout4 over limit read/write 0x00 0x1e mon_vte1_undl monitoring vte1 under limit read/write 0x00 0x13 mon_vte1_ovl monitoring vte1 over limit read/write 0x00 0x1f mon_vte2_undl monitoring vte2 under limit read/write 0x00 0x14 mon_vte2_ovl monitoring vte2 over limit read/write 0x00 0x20 mon_vts_undl monitoring vts under limit read/write 0x00 0x15 mon_vts_ovl monitoring vts over limit read/write 0x00 0x21 mon_mr1 monitoring interrupt/reset mask 1 read/write 0x00 0x22 mon_mr2 monitoring interrupt/reset mask 2 read/write 0x00 0x23 mon_ir1 monitoring interrupt/reset selection 1 read/write 0x00 0x24 mon_ir2 monitoring interrupt/reset selection 2 read/write 0x00 0x25 mon_sr1 monitoring status 1 read-only 0x00 0x26 mon_sr2 monitoring status 2 read-only 0x00 0x27 mon_vte1_curr monitoring current dac thermistor 1 read/write 0x00 0x28 mon_vte2_curr monitoring current dac thermistor 2 read/write 0x00 charge control registers 0x47 cha_mr charge mode write-only 0x00 table 4. at73c203 user interface (continued) address register name access reset state
24 at73c203 2742b?pmgmt?03/04 0x41 cha_sr charger status read-only 0x00 0x40 cha_cr charge control write-only 0x00 0x42 cha_str_cr charger safety timer control write-only 0x00 0x43 cha_str_sr charger safety timer status read-only 0x00 0x44 cha_tminon charger minimum on time read/write 0x00 0x45 cha_tminoff charger minimum off time read/write 0x00 0x46 cha_tr charger trimming read/write 0x00 table 4. at73c203 user interface (continued) address register name access reset state
25 at73c203 2742b?pmgmt?03/04 general-purpose registers chip identification register name: gp_ident access: read-only version_id: version identification these four bits correspond to device version. for the first version, version_id = 0x0. atmel_id: atmel identification these four bits give the company identification. atmel_id = 0xa note that gp_ident can only be changed by metal mask. for 56h05a and 56h05b, gp_ident = 0xa0. for 56h05c, gp_ident = 0xa2. gpio status register name: gp_gpio_read access: read-only gpio_rd_0: value of id_bits0 pin 0: id_bits0 = 0 1: id_bits0 = 1 gpio_rd_1: value of id_bits1 pin 0: id_bits1 = 0 1: id_bits1 = 1 gpio_rd_2: value of id_bits2 pin 0: id_bits2 = 0 1: id_bits2 = 1 gpio_rd_3: value of id_bits3 pin 0: id_bits3 = 0 1: id_bits3 = 1 76543210 atmel_id version_id 76543210 - - - - gpio_rd_3 gpio_rd_2 gpio_rd_1 gpio_rd_0
26 at73c203 2742b?pmgmt?03/04 gpio control register name: gp_gpio_write access: read/write gpio_oe_0: output enable for id_bits0 pin 0: id_bits0 pin configures as input 1: id_bits0 pin configures as output gpio_oe_1: output enable for id_bits1 pin 0: id_bits1 pin configures as input 1: id_bits1 pin configures as output gpio_oe_2: output enable for id_bits2 pin 0: id_bits2 pin configures as input 1: id_bits2 pin configures as output gpio_oe_3: output enable for id_bits3 pin 0: id_bits3 pin configures as input 1: id_bits3 pin configures as output gpio_do_0: output data for id_bits0 pin 0: id_bits0 pin sets to 0 (if gpio_oe_0 = 1) 1: id_bits0 pin sets to 1 (if gpio_oe_0 = 1) gpio_do_1: output data for id_bits1 pin 0: id_bits1 pin sets to 0 (if gpio_oe_1 = 1) 1: id_bits1 pin sets to 1 (if gpio_oe_1 = 1) gpio_do_2: output data for id_bits2 pin 0: id_bits2 pin sets to 0 (if gpio_oe_2 = 1) 1: id_bits2 pin sets to 1 (if gpio_oe_2 = 1) gpio_do_3: output data for id_bits3 pin 0: id_bits3 pin sets to 0 (if gpio_oe_3 = 1) 1: id_bits3 pin sets to 1 (if gpio_oe_3 = 1) 76543210 gpio_do_3 gpio_do_2 gpio_do_1 gpio_do_0 gpio_oe_3 gpio_oe_2 gpio_oe_1 gpio_oe_0
27 at73c203 2742b?pmgmt?03/04 digital rail trimming register name: dc _trim access: read/write dc_trim_1: trimming for rail 1 output voltage if seldc175 = 0: if seldc175 = 1: dc_trim_2: trimming for rail 2 output voltage if seldc25 = 0: if seldc25 = 1: 76543210 dc_trim_4 dc_trim_3 dc_trim_2 dc_trim_1 dc_trim_1 00 rail 1 output voltage = 1.2v (default value) 01 rail 1 output voltage = 1.3v 10 rail 1 output voltage = 1.1v 11 rail 1 output voltage = 1.5v dc_trim_1 00 rail 1 output voltage = 1.75v (default value) 01 rail 1 output voltage = 1.80v 10 rail 1 output voltage = 1.70v 11 rail 1 output voltage = 1.65v dc_trim_2 00 rail 2 output voltage = 1.80v (default value) 01 rail 2 output voltage = 1.85v 10 rail 2 output voltage = 1.75v 11 rail 2 output voltage = 1.70v dc_trim_2 00 rail 2 output voltage = 2.50v (default value) 01 rail 2 output voltage = 2.60v 10 rail 2 output voltage = 2.40v 11 rail 2 output voltage = 2.30v
28 at73c203 2742b?pmgmt?03/04 dc_trim_3: trimming for rail 3 output voltage dc_trim_4: trimming for rail 4 output voltage dc_trim_3 00 rail 3 output voltage = 3.3v (default value) 01 rail 3 output voltage = 3.1v 10 rail 3 output voltage = 3.2v 11 rail 3 output voltage = 3.4v dc_trim_4 00 rail 4 output voltage = 0.9v (default value) 01 rail 4 output voltage = 1.20v 10 rail 4 output voltage = 0.87v 11 rail 4 output voltage = 1.10v
29 at73c203 2742b?pmgmt?03/04 power switch control register name: pws _cr (0x4c) access: read/write with pws_force, the microprocessor can force selection of an input source. this may be used to test the at73c203 or by the microprocessor to force use of one of the batteries. pws_force: force an input source to be selected pws_enbat1: reset flatbat1 (refer to ?power switch status register? on page 30) 0: no action (default value) 1: flatbat1 is reset to 0 pws_enbat2: reset flatbat2 (refer to ?power switch status register? on page 30) 0: no action (default value) 1: flatbat2 is reset to 0 7654 3 2 1 0 ----pws_enbat2pws_enbat1pws_force pws_force input selected 0 0 power switch runs automatically (default mode) 0 1 psu 1 0 battery 2 1 1 battery 1
30 at73c203 2742b?pmgmt?03/04 power switch status register name: pws _sr access: read-only pws_status: status of the power switch with pws_status (bits accessible via spi), the microprocessor can read which supply is currently selected by the at73c203. flatbat1: bat1 flat threshold indication 0: default and reset value 1: bat1 voltage has reached flat threshold during selection (latched value). bat1 cannot be used as input source (until reset by the microprocessor) flatbat2: bat2 flat threshold indication 0: default and reset value 1: bat2 voltage has reached flat threshold during selection (latched value). bat2 cannot be used as input source (until reset by the microprocessor) 7654 3 2 1 0 ----flatbat2flatbat1pws_status pws_status input selected 0 0 power switch off or no input selected 0 1 psu 1 0 battery 2 1 1 battery 1
31 at73c203 2742b?pmgmt?03/04 usb flag status name: usb_fst access: read-only usb_fst: usb flag status 0: usb has not been used to precharge (stand alone mode) 1: usb has been used to precharge (stand alone mode) refer to ?state machine description? on page 15. usb flag control name: usb_fcr (0x4e) access: write-only usb_fcr: usb flag control 0: no action 1: resets usb_fst to 0 usb_scr: usb sleep control 0: no action 1: enter in ?usb sleep state machine? refer to ?state machine description? on page 15. 7654 3 2 1 0 ---- - - -usb_fst 7654 3 2 1 0 ---- - -usb_scrusb_fcr
32 at73c203 2742b?pmgmt?03/04 usim interface registers channel status register name: sim_csr (0x32) access: read-only rxrdy: receiver ready 0: the receiver fifo is empty. 1: at least one complete character has been received. rxfull: receiver full 0: the receiver fifo is not full. 1: the receiver fifo is full. ovre: overrun error 0: no byte has been transferred from the receive shift register to the receiver fifo when rxfull was asserted since the last reset status bits command. 1: at least one byte has been transferred from the receive shift register to the receiver fifo when rxfull was asserted since the last reset status bits command. pare: parity error 0: no parity bit has been detected as false since the last reset status bits command. 1: at least one parity bit has been detected as false since the last reset status bits command. txrdy: transmitter ready 0: the transmitter fifo is full. 1: the transmitter fifo is not full. txempty: transmitter empty 0: there are characters in either the transmitter fifo or the transmit shift register. 1: there are no characters in either the transmitter fifo or the transmit shift register. txempty is 1 after parity, stop bit and time-guard have been transmitted. txempty is 1 after stop bit has been sent, or after time-guard has been sent if sim_ttgr is not 0. txnack: non acknowledge 0: a non acknowledge has not been detected during a transmission 1: a non acknowledge has been detected during a transmission. 7654 3 2 1 0 - txnack txempty txrdy pare ovre rxfull rxrdy
33 at73c203 2742b?pmgmt?03/04 buffer status register name: sim_bsr access: read-only rxptr: receiver buffer pointer indicates the number of characters waiting to be read in the receiver fifo. if rxptr = 15 then if rxfull is set, there are 16 characters in the fifo, otherwise there are 15. txptr: transmitter buffer pointer indicates the number of characters waiting to be transmitted from the transmitter fifo. if txptr = 15 then if txrdy is set, there are 15 characters in the fifo, otherwise 16. miscellaneous status register name: sim_msr access: read-only timeout: receiver time-out 0: there has not been a time-out since the last start time-out command or the time-out register is 0. 1: there has been a time-out since the last start time-out command. iteration: max number of repetitions reached note: this bit will operate only in protocol t: 0. 0: max number of repetitions has not been reached. 1: max number of repetitions has been reached. a repetition consists of transmitted characters or successive nack. pres: sim card presence 0: the sim card is not present. 1: the sim card is present. 7654 3 2 1 0 txptr rxptr 7654 3 2 1 0 ---- -presiterationtimeout
34 at73c203 2742b?pmgmt?03/04 interrupt mask register 1 name: sim_imr1 (0x37) access: read/write rxrdy: enable rxrdy interrupt 0: disables rxrdy interrupt. 1: enables rxrdy interrupt. rxfull: enable rxfull interrupt 0: disables rxfull interrupt. 1: enables rxfull interrupt. ovre: enable overrun error interrupt 0: disables overrun error interrupt. 1: enables overrun error interrupt. pare: enable parity error interrupt 0: disables parity error interrupt. 1: enables parity error interrupt. txrdy: enable txrdy interrupt 0: disables txrdy interrupt. 1: enables txrdy interrupt. txempty: enable txempty interrupt 0: disables txempty interrupt. 1: enables txempty interrupt. txnack: enable non acknowledge interrupt 0: disables non acknowledge interrupt. 1: enables non acknowledge interrupt 7654 3 2 1 0 - txnack txempty txrdy pare ovre rxfull rxrdy
35 at73c203 2742b?pmgmt?03/04 interrupt mask register 2 name: sim_imr2 (0x39) access: read/write timeout: enable time-out interrupt 0: disables reception time-out interrupt. 1: enables reception time-out interrupt. iteration: enable iteration interrupt note: this will operate only in protocol t: 0. 0: disables iteration interrupt. 1: enables iteration interrupt. pres: enable presence interrupt 0: disables card presence interrupt. 1: enables card presence interrupt. rxhalf: enable reception buffer half full interrupt 0: disables reception buffer half full interrupt. 1: enables reception buffer half full interrupt. txhalf: enable transmission buffer half full interrupt 0: disables transmission buffer half full interrupt. 1: enables transmission buffer half full interrupt. 7654 3 2 1 0 - - - txhalf rxhalf pres iteration timeout
36 at73c203 2742b?pmgmt?03/04 mode register name: sim_mr (0x35) access: read/write tmode: protocol mode 0: protocol t: 0 1: protocol t: 1 irxnack: inhibit reception non acknowledge 0: the nack is generated 1: the nack is not generated note: this bit will be used only in protocol t: 0 receiver. dsrxnack: disable successive reception nack 0: nack is sent on the io line as soon as a parity error occurs in the received character (unless irxnack is set). 1: successive parity errors are counted up to the value specified in the max_iteration field. these parity errors gener- ate a nack on the io line. as soon as this value is reached, no additional nack is sent on the io line. the flag iteration is asserted. max_iteration: number of repetitions 0 - 7 this will operate in protocol t: 0 only bit_order 0: lsb first (direct convention) 1: msb first (inverse convention) polarity: polarity 0: odd parity (odd number of 1 on character + parity bit) (inverse convention) 1: even parity (even number of 1 on character + parity bit) (direct convention) 7654 3 2 1 0 polarity bit_order max_iteration dsrnack irxnack tmode
37 at73c203 2742b?pmgmt?03/04 control register name: sim_cr access: write-only rststa: reset status bits 0: no effect. 1: resets the status bits pare and ovre in the sim_csr. stto: start time-out 0: no effect 1: start. waiting for a character before clocking the time-out counter. rstit: reset iterations 0: no effect. 1: resets the status bit iteration. rstnack: reset non acknowledge 0: no effect 1: resets the status bit txnack. retto: rearm time-out 0: no effect 1: restart. time-out rstpres: reset presence interrupt 0: no effect 1: reset. sim card presence interrupt. rstrx: reset receiver 0: no effect 1: the receiver logic is reset and the receiver fifo is emptied. rsttx: reset transmitter 0: no effect 1: the transmitter logic is reset and the transmitter fifo is emptied. 7654 3 2 1 0 rsttx rstrx rstpres rett rstnack rstit stto rststa
38 at73c203 2742b?pmgmt?03/04 activation register name: sim_ar (0x3f) access: read/write sreset: sim reset pin 0: sim reset pin: 0. 1: sim reset pin: 1. clken: sim clock enable 0: sim clock disabled (grounded). 1: sim clock enabled. active: io line activation 0: io line at ground. 1: io line enabled. vsel: sim voltage selection 00: disabled 01: disabled 10: regulator output equals 1.8v 11: regulator output equals 2.8v 7654 3 2 1 0 - - - vsel active clken sreset
39 at73c203 2742b?pmgmt?03/04 receiver holding register name: sim_rhr (0x38) access: read-only first character received if rxrdy is set. transmitter holding register name: sim_thr (0x31) access: write-only next character to be transmitted. if transmitter fifo is full, the last character is overwritten. baud divisor register name: sim_bdr (0x3a) access: read/write the baud rate = f/(div1 x div2) where f is the sim clock frequency. div1 is coded on bdr[6]. div2 is coded on bdr[5:0]. bdr reset value = b0001100. initial baud rate = 372. 7654 3 2 1 0 rhr 7654 3 2 1 0 thr 7654 3 2 1 0 -bdr bdr[6] 0 1 div1 31 32 bdr[5:0] 0 1 - 63 div2 64 bdr[5:0]
40 at73c203 2742b?pmgmt?03/04 clock divisor register name: sim_cdr (0x3e) access: read/write the sim clock is generated through a programmable divider. the division factor can be modified in this register. cdr reset value = 0000. 7654 3 2 1 0 ---- cdr cdr[3:0] 0000 0001 to 1111 clock division factor no clock cdr[3:0]
41 at73c203 2742b?pmgmt?03/04 receiver time -out register name: sim_rtor (0x3b and 0x3c) access: read/write 0: disables the rx time-out function. 1 - 65535: the time-out counter is loaded with rtor (16 bits) when the start time-out command is given or when each new data character is received (after reception has started). transmitter time guard register name: sim_ttgr (0x3d) access: read/write time-guard duration = tg x bit period 0: disables the tx time-guard function. 1 - 255: io line is inactive high after the transmission of each character for the time-guard duration. number of errors register name: sim_ner (0x30) access: read-only nb_errors: error number during transfers this 8-bit register presents the total amount of errors that occurred during a transfer. it is a read-only register and it is r eset by reading the register. 15 14 13 12 11 10 9 8 rtor 7654 3 2 1 0 rtor 7654 3 2 1 0 ttgr 7654 3 2 1 0 ner
42 at73c203 2742b?pmgmt?03/04 voltage and temperature monitoring registers control register name: mon_cr (0x29) access: read/write mon_on: enable bit of the monitoring function 0: monitoring function disabled 1: monitoring function enabled it_reset: reset of the status register 0: no action 1: reset the status registers mon_sr1 and mon_sr2 7654 3 2 1 0 ---- - -it_resetmon_on
43 at73c203 2742b?pmgmt?03/04 vbat1 measure register name: mon_vbat1_meas (0x00) access: read-only vbat2 measure register name: mon_vbat2_meas (0x01) access: read-only usb measure register name: mon_usb_meas (0x02) access: read-only vddpsu measure register name: mon_vddpsu_meas (0x03) access: read-only 7654 3 2 1 0 mon_vbat1_meas 7654 3 2 1 0 mon_vbat2_meas 7654 3 2 1 0 mon_usb_meas 7654 3 2 1 0 mon_vddpsu_meas
44 at73c203 2742b?pmgmt?03/04 vout1 measure register name: mon_vout1_meas (0x04) access: read-only vout2 measure register name: mon_vout2_meas (0x05) access: read-only vout3 measure register name: mon_vout3_meas (0x06) access: read-only vout4 measure register name: mon_vout4_meas (0x07) access: read-only 7654 3 2 1 0 mon_vout1_meas 7654 3 2 1 0 mon_vout2_meas 7654 3 2 1 0 mon_vout3_meas 7654 3 2 1 0 mon_vout4_meas
45 at73c203 2742b?pmgmt?03/04 vte1 measure register name: mon_vte1_meas (0x08) access: read-only vte2 measure register name: mon_vte2_meas (0x09) access: read-only vts measure register name: mon_vts_meas (0x0a) access: read-only 7654 3 2 1 0 mon_vte1_meas 7654 3 2 1 0 mon_vte2_meas 7654 3 2 1 0 mon_vts_meas
46 at73c203 2742b?pmgmt?03/04 vbat1 under limit register name: mon_vbat1_undl (0x16) access: read/write vbat1 over limit register name: mon_vbat1_ovl (0x1b) access: read/write vbat2 under limit register name: mon_vbat2_undl (0x17) access: read/write vbat2 over limit register name: mon_vbat2_ovl (0x0c) access: read/write 7654 3 2 1 0 mon_vbat1_undl 7654 3 2 1 0 mon_vbat1_ovl 7654 3 2 1 0 mon_vbat2_undl 7654 3 2 1 0 mon_vbat2_ovl
47 at73c203 2742b?pmgmt?03/04 usb under limit register name: mon_usb_undl (0x18) access: read/write usb over limit register name: mon_usb_ovl (0x1d) access: read/write vddpsu under limit register name: mon_vddpsu_undl (0x19) access: read/write vddpsu over limit register name: mon_vddpsu_ovl (0x0e) access: read/write 7654 3 2 1 0 mon_usb_undl 7654 3 2 1 0 mon_usb_ovl 7654 3 2 1 0 mon_vddpsu_undl 7654 3 2 1 0 mon_vddpsu_ovl
48 at73c203 2742b?pmgmt?03/04 vout1 under limit register name: mon_vout1_undl (0x1a) access: read/write vout1 over limit register name: mon_vout1_ovl (0x1f) access: read/write vout2 under limit register name: mon_vout2_undl (0x1b) access: read/write vout2 over limit register name: mon_vout2_ovl (0x10) access: read/write 7654 3 2 1 0 mon_vout1_undl 7654 3 2 1 0 mon_vout1_ovl 7654 3 2 1 0 mon_vout2_undl 7654 3 2 1 0 mon_vout2_ovl
49 at73c203 2742b?pmgmt?03/04 vout3 under limit register name: mon_vout3_undl (0x1c) access: read/write vout3 over limit register name: mon_vout3_ovl (0x11) access: read/write vout4 under limit register name: mon_vout4_undl (0x1d) access: read/write vout4 over limit register name: mon_vout4_ovl (0x12) access: read/write 7654 3 2 1 0 mon_vout3_undl 7654 3 2 1 0 mon_vout3_ovl 7654 3 2 1 0 mon_vout4_undl 7654 3 2 1 0 mon_vout4_ovl
50 at73c203 2742b?pmgmt?03/04 vte1 under limit register name: mon_vte1_undl (0x1e) access: read/write vte1 over limit register name: mon_vte1_ovl (0x13) access: read/write vte2 under limit register name: mon_vte2_undl (0x1f) access: read/write vte2 over limit register name: mon_vte2_ovl (0x14) access: read/write vts under limit register name: mon_vts_undl (0x20 access: read/write vts over limit register name: mon_vts_ovl (0x15) access: read/write 7654 3 2 1 0 mon_vte1_undl 7654 3 2 1 0 mon_vte1_ovl 7654 3 2 1 0 mon_vte2_undl 7654 3 2 1 0 mon_vte2_ovl 7654 3 2 1 0 mon_vts_undl 7654 3 2 1 0 mon_vts_ovl
51 at73c203 2742b?pmgmt?03/04 interrupt/ reset mask register 1 name: mon_mr1 (0x21) access: read/write vbat1: enable vbat1 interrupt or reset 0: disables vbat1 interrupt or global reset. 1: enables vbat1 interrupt or global reset. vbat2: enable vbat2 interrupt 0: disables vbat2 interrupt or global reset. 1: enables vbat2 interrupt or global reset. usb: enable usb interrupt 0: disables usb interrupt or global reset. 1: enables usb interrupt or global reset. vddpsu: enable vddpsu interrupt 0: disables vddpsu interrupt or global reset. 1: enables vddpsu interrupt or global reset. vout1: enable vout1 interrupt 0: disables vout1 interrupt or global reset. 1: enables vout1 interrupt or global reset. vout2: enable vout2 interrupt 0: disables vout2 interrupt or global reset. 1: enables vout2 interrupt or global reset. vout3: enable vout3 interrupt 0: disables vout3 interrupt or global reset. 1: enables vout3 interrupt or global reset. vout4: enable vout4 interrupt 0: disables vout4 interrupt or global reset. 1: enables vout4 interrupt or global reset. 7654 3 2 1 0 vout4 vout3 vout2 vout1 vddpsu usb vbat2 vbat1
52 at73c203 2742b?pmgmt?03/04 interrupt/ reset mask register 2 name: mon_mr2 (0x22) access: read/write vte1: enable vte1 interrupt or reset 0: disables vte1 interrupt or global reset. 1: enables vte1 interrupt or global reset. vte2: enable vte2 interrupt 0: disables vte2 interrupt or global reset. 1: enables vte2 interrupt or global reset. vts: enable vts interrupt 0: disables vts interrupt or global reset. 1: enables vts interrupt or global reset. vout1comp: enable vout1comp interrupt or reset 0: disables vout1comp interrupt or global reset. 1: enables vout1comp interrupt or global reset. vout2comp: enable vout2comp interrupt or reset 0: disables vout2comp interrupt or global reset. 1: enables vout2comp interrupt or global reset. vout3comp: enable vout3comp interrupt or reset 0: disables vout3comp interrupt or global reset. 1: enables vout3comp interrupt or global reset. vout4comp: enable vout4comp interrupt or reset 0: disables vout4comp interrupt or global reset. 1: enables vout4comp interrupt or global reset. 7654 3 210 - vout4comp vout3comp vout2comp vout1comp vts vte2 vte1
53 at73c203 2742b?pmgmt?03/04 interrupt/ reset selection register 1 name: mon_ir1 (0x23) access: read/write vbat1: select for vbat1 interrupt or reset 0: interrupt selected for vbat1 1: global reset selected for vbat1. vbat2: select for vbat2 interrupt or reset 0: interrupt selected for vbat2 1: global reset selected for vbat2. usb: select for usb interrupt or reset 0: interrupt selected for usb 1: global reset selected for usb. vddpsu: select for vddpsu interrupt or reset 0: interrupt selected for vddpsu 1: global reset selected for vddpsu. vout1: select for vout1 interrupt or reset 0: interrupt selected for vout1 1: global reset selected for vout1. vout2: select for vout2 interrupt or reset 0: interrupt selected for vout2 1: global reset selected for vout2. vout3: select for vout3 interrupt or reset 0: interrupt selected for vout3 1: global reset selected for vout3. vout4: select for vout4 interrupt or reset 0: interrupt selected for vout4 1: global reset selected for vout4. 7654 3 210 vout4 vout3 vout2 vout1 vddpsu usb vbat2 vbat1
54 at73c203 2742b?pmgmt?03/04 interrupt/ reset selection register 2 name: mon_ir2 (0x24) access: read/write vte1: select for vte1 interrupt or reset 0: interrupt selected for vte1 1: global reset selected for vte1. vte2: select for vte2 interrupt or reset 0: interrupt selected for vte2 1: global reset selected for vte2. vts: select for vts interrupt or reset 0: interrupt selected for vts 1: global reset selected for vts. vout1comp: select for vout1comp interrupt or reset 0: interrupt selected for vout1comp 1: global reset selected for vout1comp. vout2comp: select for vout2comp interrupt or reset 0: interrupt selected for vout2comp 1: global reset selected for vout2comp. vout3comp: select for vout3comp interrupt or reset 0: interrupt selected for vout3comp 1: global reset selected for vout3comp. vout4comp: select for vout4comp interrupt or reset 0: interrupt selected for vout4comp 1: global reset selected for vout4comp. 7654 3 210 - vout4comp vout3comp vout2comp vout1comp vts vte2 vte1
55 at73c203 2742b?pmgmt?03/04 status register 1 name: mon_sr1 (0x25) access: read-only vbat1: vbat1 error 0 = no out-of-limit event on vbat1 since the last reset. 1 = an out-of-limit event on vbat1 has occurred since the last reset. vbat2: vbat2 error 0: no out-of-limit event on vbat2 since the last reset. 1: an out-of-limit event on vbat2 has occurred since the last reset. usb: us error 0: no out-of-limit event on usb since the last reset. 1: an out-of-limit event on usb has occurred since the last reset. vddpsu: vddpsu error 0: no out-of-limit event on vddpsu since the last reset. 1: an out-of-limit event on vddpsu has occurred since the last reset. vout1: vout1 error 0: no out-of-limit event on vout1 since the last reset. 1: an out-of-limit event on vout1 has occurred since the last reset. vout2: vout2 error 0: no out-of-limit event on vout2 since the last reset. 1: an out-of-limit event on vout2 has occurred since the last reset. vout3: vout3 error 0: no out-of-limit event on vout3 since the last reset. 1: an out-of-limit event on vout3 has occurred since the last reset. vout4: vout4 error 0: no out-of-limit event on vout4 since the last reset. 1: an out-of-limit event on vout4 has occurred since the last reset. 7654 3 210 vout4 vout3 vout2 vout1 vddpsu usb vbat2 vbat1
56 at73c203 2742b?pmgmt?03/04 status register 2 name: mon_sr2 (0x26) access: read-only vte1: vte1 error 0: no out-of-limit event on vte1 since the last reset. 1: an out-of-limit event on vte1 has occurred since the last reset vte2: vte2 error 0: no out-of-limit event on vte2 since the last reset. 1: an out-of-limit event on vte2 has occurred since the last reset vts: vts error 0: no out-of-limit event on vts since the last reset. 1: an out-of-limit event on vts has occurred since the last reset vout1comp: vout1comp error 0: no out-of-limit event on vout1comp since the last reset. 1: an out-of-limit event on vout1comp has occurred since the last reset vout2comp: vout2comp error 0: no out-of-limit event on vout2comp since the last reset. 1: an out-of-limit event on vout2comp has occurred since the last reset vout3comp: vout3comp error 0: no out-of-limit event on vout3comp since the last reset. 1: an out-of-limit event on vout3comp has occurred since the last reset vout4comp: vout4comp error 0: no out-of-limit event on vout4comp since the last reset. 1: an out-of-limit event on vout4comp has occurred since the last reset 7654 3 210 - vout4comp vout3comp vout2comp vout1comp vts vte2 vte1
57 at73c203 2742b?pmgmt?03/04 current dac thermistor 1 register name: mon_vte1_curr (0x27) access: read/write vte1curr: current programming for thermistor 1 see table 5 on page 57. vte1on: enable current dac for thermistor 1 0: disables current dac for thermistor 1: therm1 is in high impedance mode 1: enables current dac for thermistor 1 current dac thermistor 2 register name: mon_vte2_curr (0x28) access: read/write vte2curr: current programming for thermistor 2 see table 5 on page 57. vte2on: enable current dac for thermistor 2 0: disables current dac for thermistor 2: therm1 is in high impedance mode 1: enables current dac for thermistor 2 7654 3 210 - vte1on vte1curr 7654 3 210 - vte2on vte2curr table 5. current source control (vtexon = 1, x = 1 or 2) vtexcurr<5:0> x = 1 or 2 typical output current (ma) vtexcurr<5:0> x = 1 or 2 typical output current (ma) 0 000000 567 12 001100 459 1 000001 558 13 001101 450 2 000010 549 14 001110 441 3 000011 540 15 001111 432 4 000100 531 16 010000 423 5 000101 522 17 010001 414 6 000110 513 18 010010 405 7 000111 504 19 010011 396 8 001000 495 20 010100 387 9 001001 486 21 010101 378 10 001010 477 22 010110 369 11 001011 468 23 010111 360
58 at73c203 2742b?pmgmt?03/04 24 011000 351 44 101100 171 25 011001 342 45 101101 162 26 011010 333 46 101110 153 27 011011 324 47 101111 144 28 011100 315 48 110000 135 29 011101 306 49 110001 126 30 011110 297 50 110010 117 31 011111 288 51 110011 108 32 100000 279 52 110100 99 33 100001 270 53 110101 90 34 100010 261 54 110110 81 35 100011 252 55 110111 72 36 100100 243 56 111000 63 37 100101 234 57 111001 54 38 100110 225 58 111010 45 39 100111 216 59 111011 36 40 101000 207 60 111100 27 41 101001 198 61 111101 18 42 101010 189 62 111110 9 43 101011 180 63 111111 0 table 5. current source control (vtexon = 1, x = 1 or 2) (continued) vtexcurr<5:0> x = 1 or 2 typical output current (ma) vtexcurr<5:0> x = 1 or 2 typical output current (ma)
59 at73c203 2742b?pmgmt?03/04 charge control registers charger mode register name: cha_mr (0x47) access: write-only cha_ph: charger phase control 0: sets the charger control off. 1: sets battery1 to pre-conditioning charge phase. 2: sets battery2 to pre-conditioning charge phase. 3: sets battery1 and battery2 to pre-conditioning charge phase. 4: sets battery1 to fast charge phase. 5: sets battery2 to fast charge phase. 6: sets battery1 to ?pulsed? charge phase. 7: sets battery2 to ?pulsed? charge phase. 8: sets battery1 to fast charge phase and battery 2 to pre-conditioning charge phase. 9: sets battery2 to fast charge phase and battery 1 to pre-conditioning charge phase. a: sets battery1 to ?pulsed? charge phase and battery 2 to pre-conditioning charge phase. b: sets battery2 to ?pulsed? charge phase and battery 1 to pre-conditioning charge phase. c: not used d: not used e: not used f: not used cha_usb_psu: charger usb/psu selection 0: psu is selected. 1: usb is selected. cha_curr: charger current control 0: sets the current to 100ma. 1: sets the current to 200ma. 2: sets the current to 300ma. 3: sets the current to 500ma. 7654 3210 cha_curr cha_usb_psu cha_ph
60 at73c203 2742b?pmgmt?03/04 charger status register name: cha_sr (0x41) access: read-only cha_ph: charger phase control 0: the charger control is off. 1: battery1 in pre-conditioning charge phase. 2: battery2 in pre-conditioning charge phase. 3: battery1 and battery2 in pre-conditioning charge phase. 4: battery1 in fast charge phase. 5: battery2 in fast charge phase. 6: battery1 in ?pulsed? charge phase. 7: battery2 in ?pulsed? charge phase. 8: battery1 in fast charge phase and battery 2 in pre-conditioning charge phase. 9: battery2 in fast charge phase and battery 1 in pre-conditioning charge phase. a: battery1 in ?pulsed? charge phase and battery 2 in pre-conditioning charge phase. b: battery2 in ?pulsed? charge phase and battery 1 in pre-conditioning charge phase. c: not used d: not used e: not used f: not used cha_usb_psu: charger usb/psu selection 0: psu selected. 1: usb selected. cha_curr: charger current control 0: current selected: 100ma. 1: current selected: 200ma. 2: current selected: 300ma. 3: current selected: 500ma. cha_st_timer: charger safety timer status 0: no interrupt or timer disabled. 1: an interrupt (end of timer) has occurred. 765 4 3210 ch_st_timer cha_curr cha_usb_psu cha_ph
61 at73c203 2742b?pmgmt?03/04 charger control register name: cha_cr (0x40) access: write-only rea_wdog: rearm the watchdog 0: no action 1: rearms the watchdog sta_tim: start the safety timer 0: no action 1: starts the safety timer res_tim_it: reset the safety timer interrupt 0: no action 1: resets the safety timer interrupt res_cha_it: reset the charger interrupt 0: no action 1: resets the charger interrupt 7654 3 2 1 0 ----res_cha_itres_tim_itsta_timrea_wdog
62 at73c203 2742b?pmgmt?03/04 charger safety timer control register name: cha_str_cr (0x42) access: write-only cha_str_cr: charger safety timer control register safety timer = cha_str_pr x 210 sec. writing 0x00 in this register disables the safety timer. thus the safety timer can be programmed from 0 to 53477 sec. (14h 51min). charger safety timer status register name: cha_str_sr (0x43) access: read-only cha_str_sr: charger safety timer register safety timer = cha_str_sr x 210 sec. it gives the status of the internal counter from 0 to 53477 sec. (14h 51min). charger minimum on time register name: cha_tminon (0x44) access: read/write cha_tminon: minimum on time for pulsed charge phase minimum on-time = cha_tminon *2 ms thus the minimum on-time can be tuned from 0 to 510 ms. 7654 3 2 1 0 cha_str 7654 3 2 1 0 cha_str_sr 7654 3 2 1 0 cha_tminon
63 at73c203 2742b?pmgmt?03/04 charger minimum off time register name: cha_tminoff (0x45) access: read/write cha_tminoff: minimum on time for pulsed charge phase minimum on-time = cha_tminoff *2 ms thus the minimum off-time can be tuned from 0 to 510 ms. charger trim register name: cha_tr (0x46) access: read/write cha_volt_trim: charger voltage trimming 0: set the regulation voltage to 4.20v (typical). 1: set the regulation voltage to 4.17v (typical). 2: set the regulation voltage to 4.13v (typical). 3: set the regulation voltage to 4.10v (typical). 4: set the regulation voltage to 4.23v (typical). 5: set the regulation voltage to 4.26v (typical). 6: set the regulation voltage to 4.30v (typical). 7: set the regulation voltage to 4.07v (typical). cha_duty: charger duty cycle for pulsed charge phase duty ratio threshold of ?on? cycles to ?off? cycles 0: duty cycle threshold: 1/4 1: duty cycle threshold: 1/8 2: duty cycle threshold: 1/16 3: duty cycle threshold: 1/32 4: duty cycle threshold: 1/64 5: duty cycle threshold: 1/128 6: duty cycle threshold: 1/256 7: duty cycle threshold: 1/512 7654 3 2 1 0 cha_tminoff 7654 3 2 1 0 - - cha_duty cha_volt_trim
64 at73c203 2742b?pmgmt?03/04 block description table 6. digital pin description list name input/output por state level current capability (ma) description sclk input gnddig - vout3 spi clock input nsen input with 100 k pull-up gnddig - vout3 spi clock select 0: spi selected 1: spi unselected sdi input gnddig - vout3 spi data input sdo output hiz gnddig - vout3 2 spi data output button_out output gnd gnddig - vout3 1 state of the button sent to the microprocessor 0: button unpressed or global reset active 1: button pressed button_in input with 100 k pull-down gnddig - vsauv input connecting to the button 0: button unpressed 1: button pressed power_en input gnddig - vout3 input coming from the microprocessor to put off the at73c203 0: at73c203 forced in off mode (ignored during global reset) 1: no action nint output vout3 gnddig - vout3 1 interrupt output to warn the microprocessor 0: an interrupt occurred 1: no interrupt occurred chg_inhibit input gnddig - vout3 inhibit charger input. 0: no action 1: charger is stopped nshutdown input with 100 k pull-up gnddig - vsauv asynchronous reset 0: at73c203 in reset (including the digital block) 1: no action nproc_reset output gnd gnddig - vout3 1 reset output for the microprocessor 0: reset active 1: reset inactive nproc_reset_ out input gnddig - vout3 reset input board_reset output vout3 gnddig - vout3 1 reset output nboard_reset output gnd gnddig - vout3 1 reset output nasic_reset output gnd gnddig - vout3 1 reset output nasic_reset_ request input gnddig - vout3 reset input
65 at73c203 2742b?pmgmt?03/04 idbits0 input/output with 100 k pull- down gnddig - vout3 1 by default: used as input (must be connected to gnd or vout3) can be configured as output idbits1 input/output with 100 k pull- down gnddig - vout3 1 by default: used as input (must be connected to gnd or vout3) can be configured as output idbits2 input/output with 100 k pull- down gnddig - vout3 1 by default: used as input (must be connected to gnd or vout3) can be configured as output portest output avss-vswin pin used for test por must be left unconnected idbits3 input/output with 100 k pull- down gnddig - vout3 1 by default: used as input (must be connected to gnd or vout3) can be configured as output seldc25 input gnddig - vsauv voltage rail 2 selection seldc175 input gnddig - vsauv voltage rail 1 selection nen_rail3 input gnddig - vsauv enable rail 3 (read at start-up) 0: rail 3 enabled 1: rail 3 disabled nen_rail4 input gnddig - vsauv enable rail 4 (read at start-up) 0: rail 4 enabled 1: rail 4 disabled pcmcia input gnddig - vsauv input to configure the threshold of the power switch controller to consider psu to be present 0: threshold = 4.7 - 4.3v 1: threshold = 2.9v - 2.7v see section 4.2. sim_pres input with 100 k pull-down gnddig - vsauv card presence detection contact input to be used with a normally open presence switch 0: no card connected 1: card connected nusim_int output gnddig - vout3 1 usim interrupt output 0: an usim interrupt occurred 1: no usim interrupt occurred syst_clk input with 100 k pull-down gnddig - vout3 clock input from the microprocessor. the frequency of syst_clk must be at least two times superior to sclk. maximum frequency: 13 mhz. syst_clk duty cycle must be better than 30%-70%. table 6. digital pin description list name input/output por state level current capability (ma) description
66 at73c203 2742b?pmgmt?03/04 sim_io input/output off gnddig - vsim respects the ets ts 102 221 v4.2.0 standard usim bidirectional interface line sim_reset output gnddig - vsim respects the ets ts 102 221 v4.2.0 standard usim reset line sim_clk output off gnddig - vsim respects the ets ts 102 221 v4.2.0 standard usim clock line vreffuse input with 550 k pull-down avss-vswin pin used for test mode and to blow up fuses. must be connected to ground scan_test_md input with 100 k pull-down gnddig - vsauv pin for test. must be connected to ground scan_enable input with 100 k pull-down gnddig - vsauv pin for test. must be connected to ground test1 input/output (input only in functional mode) gnddig - vsauv pin used for test. but also: test1 = 0: rail1 enabled test1 = 1: rail1 disabled test2 input/output (input only in functional mode) gnddig - vsauv pin used for test. but also: test2 = 0: rail2 enabled test2 = 1: rail2 disabled table 7. for digital pins referred to vout3 symbol parameter conditions v dd min max units v il low level input voltage guaranteed input low voltage from 3.0v to 3.5v -0.3 0.3 x v dd v v ih high level input voltage guaranteed input high voltage from 3.0v to 3.5v 0.7 x v dd v dd + 0.3 v v ol low level output voltage i ol = 1 ma or 2 ma depending on the pin (see table 6) from 3.0v to 3.5v 0.4 v v oh high level output voltage i oh = 1 ma or 2 ma depending on the pin (see table 6) from 3.0v to 3.5v 2.4 v table 6. digital pin description list name input/output por state level current capability (ma) description
67 at73c203 2742b?pmgmt?03/04 table 8. for digital pins referred to vsauv symbol parameter conditions v dd min max units v il low level input voltage guaranteed input low voltage from 2.4v to 2.6v -0.3 0.3 x v dd v v ih high level input voltage guaranteed input high voltage from 2.4v to 2.6v 0.7 x v dd v dd + 0.3 v v ol low level output voltage i ol = 1 ma or 2 ma depending on the pin (see table 6) from 2.4v to 2.6v 0.4 v v oh high level output voltage i oh = 1 ma or 2 ma depending on the pin (see table 6) from 2.4v to 2.6v 1.6 v
68 at73c203 2742b?pmgmt?03/04 electrical characteristics power switch the power switch control block drives external dual pmos devices to multiplex v ddpsu from battery 1 (bat1), battery 2 (bat2) and an ac/dc power supply unit (psuin). the purpose of this cell is to guarantee a sufficient supply for v ddpsu and to limit drops even during switchover. inrush current from source to v ddpsu must be avoided. back powering from a selected power source to all other power sources must be avoided. figure 13. power switch controller note: 1. print is internal to the at73c203. c16 c17 c18 c19 c20 t1 t2 t3 maxsupply v ddpsu gabat2 gabat1 gapsu psu_pio bat2_pio bat1_pio psu b at 1 b at 2 d2 d3 usb usb_pio vsw_in vsw power switch controller rint (1) c12
69 at73c203 2742b?pmgmt?03/04 automatic selection when the power switch digital control block is off, v ddpsu is set to the high impedance state. the supply of this cell comes from an analog or done with four external schottky diodes connected to bat_1pio, bat2_pio, psu_pio and usb_in. the system should respect the ?universal seri al bus specification?, especially section 7.2.4.1, which specifies that the maximum equivalent load seen by the usb is 10 f in parallel with 44 ohms. when the cell is on, the power switch must automatically select the correct power source. psu is a non current-limited 5v supply output. bat2 is a lithium ion battery and can be removed. bat1 is a lithium ion battery and is always soldered to the pcb. a selection priority rule is used: psu > bat2 > bat1 when the psu is plugged in, it is selected by default. if the psu is not plugged in, bat2 is used if it is present and has enough voltage. if psu is not plugged in, and bat2 is unplugged or below the flat threshold, bat1 is used if bat1?s voltage is high enough. for a critical situation on any of the power sources, the automatic switching shall ensure that v ddpsu stays within specifications. this means that the automatic supply selection fets must be switched as quickly as possible, ideally with a maximum switchover of 1 s (max: 5 s) and guarantee that the already enabled fets are switched off before the newly selected fets are switched on. the faster the switching, the smaller the capacitance required to hold up v ddpsu (target: 100 f max). to handle all cases, fast analog comparators on each input with appropriate hysteresis (in voltage and in time) must be used within the at73c203. to meet the 5 s requirement, the comparator must be fast enough to detect when a source is disconnected (or a low voltage threshold is reached) but slow enough when detecting that a new source is plugged in (depending on contact bounce during the insertion/removal of a power source). the slow delay is done with the 10 khz internal oscillator. at start-up, the cell is off and is turned on by the internal digital block. with pws_cr register (bits accessible via spi), the application processor can force an input source to be selected. this may be used for testing the at73c203 or by the appli- cation processor to force use of one of the batteries. using pws_sr register, the application processor can read which supply is currently selected by the at73c203. if one input is not used (psu, bat1 or bat2), it can be grounded. the corresponding unused output (gapsu, gabat1 or gabat2) can be left unconnected in this case.
70 at73c203 2742b?pmgmt?03/04 power switch controller electrical specifications table 9. power switch controller electrical specifications symbol parameter condition min typ max unit top operating temperature -20 +85 c psupio charger supply voltage 55.5v b at 2 p i o battery 2 supply voltage 3.6 4.35 v b at 1 p i o battery 1 supply voltage 3.6 4.35 v i psu current load on v ddpsu 2a i cc current consumption onpio = 1, psupio = 5.5v, b at 2 p i o = 4.35v and b at 1 p i o = 4.35v. 500 ua i off off current onpio = 0 and precharg = 0 30 a t sw switching time between two sources 1 5 s v ddpsumin minimum voltage on v ddpsu onpio = 1, input selected = 3.1v 2.85 v t startup time to start 50 100 s t precharege time to precharge the v ddpsu capacitor onpio = 0 and precharg = 1, external load on v ddpsu = 100 a 100 ms t deboun_psu time for debouncing the psu presence 100 ms t deboun_bat2 time for debouncing the bat2 presence 100 ms psupio_r1 voltage to consider psu plugged in rising, v bg = 1.23v, pcmcia = 0 3.43 v psupio_f1 voltage to consider psu removed falling, v bg = 1.23v, pcmcia = 0 2.96 v psupio_hy1 psu hysteresis input hysteresis, pcmcia = 0 470 mv psupio_r2 voltage to consider psu plugged in rising, v bg = 1.23v, pcmcia = 1 3.05 v psupio_f2 voltage to consider psu removed falling, v bg = 1.23v, pcmcia = 1 2.80 v psupio_hy2 psu hysteresis input hysteresis, pcmcia = 1 250 mv bat2pio_r voltage to consider bat2 available rising, v bg = 1.23v 3.20 v bat2pio_f voltage to consider bat2 removed or flat falling, v bg = 1.23v 2.95 v bat2pio_hy bat2 hysteresis input hysteresis 250 mv bat1pio_r voltage to consider bat1 available rising, v bg = 1.23v 3.20 v bat1pio_f voltage to consider bat1 removed or flat falling, v bg = 1.23v 2.95 v bat1pio_hy bat1 hysteresis input hysteresis 250 mv
71 at73c203 2742b?pmgmt?03/04 serial peripheral interface (spi) the spi interface between the system and the at73c203 is detailed in figure 14. figure 14. spi architecture register bank sdi nsen sclk sdo sdo sdo_en sclk nsen sdi sdi_select reset a6 a0 d7 d0 spi_core r/w write control read control 8 8 reg_in addr write reg_out 7 3 sdo_select d7 d0 write_data_buffer
72 at73c203 2742b?pmgmt?03/04 protocol the spi is a 4-wire bidirectional asynchronous serial link providing 128 x 8 register access by the microprocessor. the spi operates in slave mode only. the spi protocol is shown in figure 15. figure 15. spi protocol on sdi, the first bit is read/write. ?0? indicates a write operation while ?1? denotes a read operation. the seven following bits are used for the register address and the eight that follow are the write data. for both address and data, the most significant bit is the first one. in case of a read operation, sdo first provides the contents of the read register, msb. the transfer is enabled by the nsen signal active low. when the spi is not operating, sdo output is set to high impedance to allow sharing of the cpu serial interface with other devices. the interface is reset at every rising edge of nsen in order to return to an idle state, even if the transfer does not succeed. the spi is synchronized with the serial clock sclk. falling edge latches sdi input and rising edge shifts sdo output bits. nsen sclk sdi sdo rw a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
73 at73c203 2742b?pmgmt?03/04 timing for spi interface spi interface timings are shown in figure 16. figure 16. spi interface timing diagram note: 1. t sysclk = system clock period . the frequency of sys_clk must be at least two times superior to that of sclk. after the end of reset (nproc_reset = 1), sys_clk must run at least during 500 s before the first spi access. the minimum time for the usim is one system clock period (t sysclk ). as the clock domain is 900 khz, to monitor function registers, two consecutive accesses at the same register must be superior to the 900 khz period. otherwise, only the second access will be taken into account. the same approach is used for the charger registers but with 10 khz. n sen sclk sdi sdo t ssen t c t wl t ssdi t hsdi t dsdo t hsdo t wh t hsen table 10. spi timing parameters timing parameter description min max t c sclk min period (1) t sysclk /2 t wl sclk min pulse width low 50 ns - t wh sclk min pulse width high 50 ns - t ssen setup time sen falling to sclk rising 50 ns - t hsen hold time sclk falling to sen rising t sysclk - t ssdi setup time sdi valid to sclk falling 20 ns - t hsdi hold time sclk falling to sdi not valid 20 ns - t dsdo delay time sclk rising to sdo valid - 20 ns t hsdo hold time sclk rising to sdo not valid 0 ns -
74 at73c203 2742b?pmgmt?03/04 rail1 dc/dc converter 1.20v, 1.2a rail1 is a programmable buck dc/dc converter dedicated to the application processor core supply. the default voltage is 1.20v. three other values can be programmed: 1.3v, 1.1v and 1.5v. an external pin can select 1.75v (seldc175) output voltage with tuning: 1.80v, 1.70v and 1.65v. the entire cell is optimized for 1.20v. when the cell is off, the output is pulled to ground. the application processor can change the output voltage, as stated above, via registers accessible by the spi. figure 17. rail1 schematic seldc175 trim dc1[1:0] on dc1 clk_dc1 vddpsu1 dcsense1 dl1 dl1 vout1 dc/dc converter 1.2 v, 1.2a r1 c1 l1 t4 c2 table 11. rail1 external components schematic reference reference c1 22 f ceramic capacitor c2 47 f tantalum low esr tpsw476m010r0150 capacitor or equivalent l1 4.7 h: smt3106-471m (gowanda) r1 100 m ? 2% 250 mw t4 si5513dc
75 at73c203 2742b?pmgmt?03/04 rail1 electrical specifications rail1 can operate up to a load of 1.5 a if the r1 resistor is replaced by 80 m ? 2%. rail 1 can also operate at v in = 2.85v. table 12. rail1 electrical specifications symbol parameter condition (1.2v selected) min typ max unit v in operating supply voltage 2.97 5.5 v temperature range -20 85 c v out output voltage 0 < i load < 1200 ma, 3v < v in < 5.5v 1.2 v i out output current 120 0 ma ripple voltage 40 mv eff36 efficiency v in = 3.6v, i load = 600 ma 83 % eff50 efficiency v in = 5v, i load = 600 ma 85 % static line regulation t r = t f = 5 s, v in from 3v to 5.5v i load = 1200 ma 25 mv static load regulation t r = t f = 5 s, v in = 3v and v in =5.5v i load from 0 to 1200 ma 10 mv transient line regulation t r = t f = 5 s, v in from 3v to 5.5v i load = 1200 ma 35 mv transient load regulation t r = t f = 5 s, v in = 3v and v in = 5.5v i load from 0 to 1200 ma 80 mv i cc powerdown current v in = 5.5v 1 a t r rise time i load = 400 ma 0.01 10 ms t r1200 rise time i load = 1200 ma 0.01 15 ms t settle settling time for programmed voltage switching full load, 0.85v to 1.3v condition 70 s i sc limitation current 3v < v in < 5.5v 1.2 a
76 at73c203 2742b?pmgmt?03/04 rail2 dc/dc converter 1.8v, 1.2 a rail2 is a programmable buck dc/dc converter dedicated to digital supply. the default voltage is 1.8v. three other values can be programmed: 1.85v, 1.75v and 1.70v. an external pin can select 2.5v output voltage (seldc25) tuning: 2.6v, 2.4v and 2.3v. the entire cell is optimized for 1.8v when the cell is off, the output is in high impedance state. the application processor can change the output voltage, as stated above, via registers accessible by the spi. figure 18. rail2 schematic seldc25 trim dc2[1:0] on dc2 clk_dc2 vddpsu2 dcsense2 dh2 dl2 vout2 dc/dc converter 1.8v, 1.2a r2 c3 l2 t5 c4 table 13. rail2 external components schematic reference reference c3 22 f ceramic capacitor c4 47 f tantalum low esr tpsw476m010r0150 capacitors or equivalent l2 10 h: smt3106-102m (gowanda) r2 100 m ? 2% 250 mw t5 si5513dc
77 at73c203 2742b?pmgmt?03/04 rail2 electrical specifications rail 2 can also operate at v in = 2.85v. table 14. rail2 electrical specifications symbol parameter condition (1.2v selected) min typ max uni t v in operating supply voltage 2.97 5.5 v temperature range -20 85 c v out output voltage 0 < i load < 1200 ma, 3v < v in < 5.5v 1.8 v i out output current 120 0 ma ripple voltage i load = 1.2 a, v in = 3.6v 200 mv eff36 efficiency v in = 3.6v, i load = 600 ma 85 % eff50 efficiency v in = 5v, i load = 600 ma 87 % static line regulation t r = t f = 5 s, v in from 3v to 5.5v, i load = 1200 ma 25 mv static load regulation t r = t f = 5 s, v in = 3v and v in = 5.5v, i load from 0 to 1200 ma 10 mv transient line regulation t r = t f = 5 s, v in from 3v to 5.5v, i load = 1200 ma 35 mv transient load regulation t r = t f = 5 s, v in = 3v and v in = 5.5v, i load from 0 to 1200 ma 80 mv i cc powerdown current v in = 5.5v 1 a t r rise time i load = 1200 ma 100 0 ms t settle settling time for programmed voltage switching full load, 0.85v to 1.3v condition 50 s i sc limitation current 3v < v in < 5.5v 1.2 2 a
78 at73c203 2742b?pmgmt?03/04 rail3 dc/dc converter 3.3v, 520 ma rail3 is a programmable buck dc/dc converter followed by a linear drop out regulator. the default value of the ldo is 3.3v. three other values can be programmed: 3.1v, 3.2v and 3.4v. the entire cell is optimized for 3.3v. when the cell is off, the output is pulled to ground. the application processor can change the output voltage, as stated above, via registers accessible by the spi. figure 19. rail3 schematic trim dc3[1:0] on dc2 clk_dc2 vddpsu3 dcsense3 vboost dh3 dl3 vout3 dc/dc converter 3.3v, 520 ma l3 c5 t7 c7 ldo 3.3 v t6 c6 r3 d1 table 15. rail3 external components schematic reference reference c5, 22 f ceramic capacitor c6, c7 47 f tantalum low esr tpsw476m010r0150 capacitor or equivalent d1 schottky diode: mbra120lt3 (on semiconductor) l3 10 h: smt3106-102m (gowanda) r3 100 m ? 2% 250 mw t6 si1400dl t7 si8401dl
79 at73c203 2742b?pmgmt?03/04 rail3 electrical specifications rail 3 can also operate at v in = 2.85v. table 16. rail3 electrical specifications symbol parameter condition (3.3v selected) min typ max uni t v in operating supply voltage 2.97 5.5 v temperature range -20 85 c v out output voltage 0 < i load < 520 ma, 3v < v in < 5.5v 520 v i out output current 120 0 ma ripple voltage 70 mv eff36 efficiency v in = 3.6v, i load = 430 ma 73 % eff50 efficiency v in = 5v, i load = 430 ma 65 % static line regulation t r = t f = 5 s, v in from 3v to 5.5v, i load = 430 ma 30 mv static load regulation t r = t f = 5 s, v in = 3v and v in = 5.5v, i load from 52 to 468 ma 20 mv transient line regulation t r = t f = 5 s, v in from 3v to 5.5v, i load = 300 ma 80 mv transient load regulation t r = t f = 5 s, v in = 3v and v in = 5.5v, i load from 0 to 300 ma 70 mv i cc powerdown current v in = 5.5v 1 a t r rise time i load = 400 ma 0.01 100 ms t settle settling time for programmed voltage switching full load, 3.1v to 3.4v condition 500 s i sc limitation current 3v < v in < 5.5v 520 850 ma
80 at73c203 2742b?pmgmt?03/04 rail 4 dc/dc converter 0.9v, 1.2a rail4 is a programmable buck dc/dc converter dedicated to the supply of advanced core processing units. the default voltage is 0.9v. three other values can be pro- grammed: 1.2v, 0.87v and 1.1v. the entire cell is optimized for 0.9v. when the cell is off, the output is in high impedance state. the application processor can change the output voltage, as stated above, via registers accessible by the spi. figure 20. rail4 schematic trim dc4[1:0] on dc4 clk_dc4 vddpsu4 dcsense4 dh4 dl4 vout4 dc/dc converter 0.9v, 1.2a r4 c8 l4 t8 c9 table 17. rail4 external components schematic reference reference c8, 22 f ceramic capacitor c9 47 f tantalum low esr tpsw476m010r0150 capacitor or equivalent l4 4.7 h: smt3106-47m (gowanda) r4 100 m ? 2% 250 mw t8 si5513dc
81 at73c203 2742b?pmgmt?03/04 rail4 electrical specifications rail 4 can also operate at v in = 2.85v. table 18. rail4 electrical specifications symbol parameter condition (0.9v selected) min typ max uni t v in operating supply voltage 2.97 5.5 v temperature range -20 85 c v out output voltage 0 < i load < 1200 ma, 3v < v in < 5.5v 0.9 v i out output current 120 0 ma ripple voltage i load = 1.2 a, v in = 3.6v 35 mv eff36 efficiency v in = 3.6v, i load = 600 ma 78 % eff50 efficiency v in = 5v, i load = 600 ma 80 % static line regulation t r = t f = 5 s, v in from 3v to 5.5v, i load = 1200 ma 20 mv static load regulation t r = t f = 5 s, v in = 3v and v in = 5.5v, i load from 120 to 1200 ma 10 mv transient line regulation t r = t f = 5 s, v in from 3v to 5.5v, i load = 1200 ma 35 mv transient load regulation t r = t f = 5 s, v in = 3v and v in = 5.5v, i load from 120 to 1200 ma 85 mv i cc powerdown current v in = 5.5v 1 a t r rise time i load = 1200 ma 300 0 s tsettle settling time for programmed voltage switching full load, 0.84v to 0.93v condition 50 s i sc limitation current 3v < v in < 5.5v 120 0 2ma
82 at73c203 2742b?pmgmt?03/04 900 khz oscillator and clock distribution the 900 khz oscillator provides the clock to all dc/dc converters. the clock distributor provides phased clocks to the dc/dc converters to avoid them switching at the same time. figure 21. 900 khz oscillator distribution rail4 oscillator rail3 oscillator rail2 oscillator rail1 oscillator 900 khz oscillator
83 at73c203 2742b?pmgmt?03/04 voltage and temperature monitoring function the at73c203 integrates voltage monitoring and temperature monitoring functional- ities, thus enabling the application processor to know when an under-voltage or over- temperature error condition occurs. the application processor can control this situation by changing the thresholds and programming an interrupt or a reset in the event an error condition occurs. all the controls are performed via registers accessed via the spi. figure 22. voltage and temperature monitoring architecture voltage reference interuption reset vout1 vout2 vout3 vout4 vbat1 vbat2 usb vddpsu vout1 vout2 vout3 vout4 therm1 therm2 vmes t? t? vte1 vte2 vts temperature sensor multiplexer and attenuators status registers 8 bits adc it or reset registers mask registers over limit registers under limit registers measure registers current register
84 at73c203 2742b?pmgmt?03/04 analog to digital converter and multiplexer an internal 8-bit analog to digital converter is used to measure the different voltages. the analog to digital converter has eleven internal inputs listed as follows: v bat1 (internal battery) v bat2 (external battery) usb (usb supply) v ddpsu (output of the power switch) v out1 (output of rail1) v out2 (output of rail2) v out3 (output of rail3) v out4 (output of rail4) v te1 (voltage on thermistor 1) v te2 (voltage on thermistor 2) v ts (output of the internal temperature sensor) an external capacitor (c21) on v mes pin enables filtering of the adc input and provides immunity to high frequency noise. these inputs are multiplexed into the analog to digital converter. this has a resolution of eight bits. the basic input range is 0.6v to 2.25v (typical) but the inputs have built-in attenuators to allow measurements without external components. take note that no attenuator is present for v out1 , v out4 , v te1 , v te2 and v ts .
85 at73c203 2742b?pmgmt?03/04 voltage and temperature monitoring electrical characteristics all bridge resistance values are given with 30% of global variations and mismatch val- ues of less than 1%. all ratios will be confirmed during the design process. typical sensor characteristic law: table 19. bridge monitoring (attenuators) electrical specifications symbol parameter condition min typ max r at b at 1 ratio v bat1 0v 5.5v 2.5 r at b at 2 ratio v bat2 0v 5.5v 2.5 r at us b ratio usb 0v 5.5v 2.5 r vddpsu ratio v ddpsu 0v 2.5v 2.5 r out2 ratio v out2 0v 3.4v 2.0 r out3 ratio v out3 0v 5.5v 2.0 v t () 1.31 3.6 10 3 ? t 27 ? () ? = table 20. temperature sensor electrical specifications symbol parameter condition min typ max units v cc supply voltage 2.4 2.5 2.6 v i cc supply current v cc = 2.5v 100 a dj temperature sense dynamic 0 80 c t absolute error ? = 55 c 10 c ? t/ ?? differential error 10% - 90%, ?? = [45 c, 55 c] 5% v/ ? voltage dynamic range 10% - 90%, ?? = [0 c, 80 c] 1 v ? v/ ?? sensor voltage sensitivity 1 20 mv/ c v tnom sensor output voltage @27 c ? = 27 c1.231.33v
86 at73c203 2742b?pmgmt?03/04 figure 23. typical sensor characteristics digital core function by default, the digital core function is disabled. to enable it, the mon_on bit in register mon_cr must be set to 1. a transition from 0 to 1 of mon_on resets all the internal registers. when the digital core function is on, the internal digital core automatically starts the monitoring sequence. it cycles sequentially through the measurement of the analog inputs. eight measurements are taken, then the digital core computes the average of these eight values to reduce noise before moving to the next input. average values from these inputs are stored in value registers. see table 21. these can be read out through the spi bus. measurements are updated every 2 ms (approximate). to assure better accuracy, a calibration should be made during the printed circuit board test by injecting an accurate voltage into the analog inputs and checking the voltage read by the adc. by comparing the voltage read by the adc to the theoretical value stored in an external flash memory, the software can remove the internal offset. table 21. value registers mon_vbat1_meas mon_vout3_meas mon_vbat2_meas mon_vout4_meas mon_usb_meas mon_vte1_meas mon_vddpsu_meas mon_vte2_meas mon_vout1_meas mon_vts_meas mon_vout2_meas
87 at73c203 2742b?pmgmt?03/04 an automatic comparison is launched when the monitoring function is enabled. the dig- ital core compares the measurement with programmed limits stored in the limit registers. see table 22 . the results of out-of-limit comparisons are stored in the status registers (see table 23 on page 87), which can be read over the spi to flag an out-of-limit condition. when an out-of-limit comparison occurs, an interrupt or a reset can be programmed via mask and interrupt/reset registers. see table 24. thermistor measurement two external ntc thermistors are used to measure the temperature of the battery. the resistance of the ntc is proportional to the temperature. to measure the resistance and determine the temperature two 6-bit current dacs are integrated into the at73c203. the software can program the current flowing through thermistors 1 and 2 via mon_vte1_curr and mon_vte2_curr registers and can then read back the volt- age through mon_vte1_meas and mon_vte2 _meas registers. the temperature can then be estimated by the microprocessor. table 22. limit registers mon_vbat1_undl mon_vbat1_ovl mon_vbat2_undl mon_vbat2_ovl mon_usb_undl mon_usb_ovl mon_vddpsu_undl mon_vddpsu_ovl mon_vout1_undl mon_vout1_ovl mon_vout2_undl mon_vout2_ovl mon_vout3_undl mon_vout3_ovl mon_vout4_undl mon_vout4_ovl mon_vte1_undl mon_vte1_ovl mon_vte2_undl mon_vte2_ovl mon_vts_undl mon_vts_ovl table 23. status registers mon_sr1 mon_sr2 table 24. mask and interrupt /reset registers mon_mr1 mon_ir1 mon_mr2 mon_ir2
88 at73c203 2742b?pmgmt?03/04 current dac electrical specifications the 6-bit dac parameters are shown in table 25 below. comparator electrical specifications in parallel to the dac, a comparator for each digital core supply rail (v out1 , v out2 , v out3 and v out4 ) is used as a real time supply rail brownout detector for a drop. the value of the comparator is not programmable but the threshold moves according to the voltage chosen. (refer to the dc/dc converter specifications specific to each supply rail.) usim interface a low drop out (ldo) voltage regulator provides an accurate power supply to the sim card. two nominal values can be programmed: 1.8v or 2.8v. it is supplied by v ddpsu . when the cell is off, the output is pulled to ground. the application processor can change the output voltage, as stated above, via registers accessible by the spi. figure 24. usim regulator external components: 2.2 fx5r 10% output capacitor table 25. current dac electrical specifications symbol parameter condition min typ max units v texcurr<0> v texcurr<0> 67.59 a v texcurr<1> v texcurr<1> 12 15 18 a v texcurr<2> v texcurr<2> 24 30 36 a v texcurr<3> v texcurr<3> 48 60 72 a v texcurr<4> v texcurr<4> 96 120 144 a v texcurr<5> v texcurr<5> 192 240 288 a lincurr linearity i out = f(rl) rl: resistive load to ground v out = 0 to 2.35v 2 % table 26. comparator electrical specifications symbol parameter condition min typ max units v out1comp v out1 threshold 8 % v out2comp v out2 threshold 8 % v out3comp v out3 threshold 7 % v out4comp v out4 threshold 8 % sim regulator 1.8 v 30 ma/2.8 v 50 ma sim_vcc c13
89 at73c203 2742b?pmgmt?03/04 usim 1.8v regulator electrical specifications the usim 1.8v regulator complies with ets ts 102 221, sections 5 and 6. usim 2.8v regulator electrical specifications the usim 2.8v regulator complies with ets ts 102 221, sections 5 and 6. table 27. usim 1.8v regulator electrical specifications symbol parameter condition min typ max units v ddsim operating supply voltage 2.97 5.5 v temperature range -20 85 c v sim output voltage 0 < i load < 30 ma, 3v < v ddsim < 5.5v 1.75 1.80 1.85 v i out output current 30 ma v drop min supply for sim_vcc > 1.75v i load = 50 ma 1.90 v transient line regulation t r = t f = 5 s, v ddsim from 3v to 5.5v, i load = 30 ma 40 mv transient load regulation t r = t f = 5 s, v in = 2.97v, i load from 3 to 27 ma 40 mv i cc quiescent current v ddsim = 5.5v 50 a i cc powerdown current v ddsim = 5.5v 1 a t r rise time i load = 30 ma 10% - 90% v out 500 s i sc limitation current 3v < v ddsim < 5.5v 30 ma v n output noise bw: 10 hz to 100 khz including bandgap noise 1 mvrms table 28. usim 2.8v regulator electrical specifications symbol parameter condition min typ max units v ddsim operating supply voltage 2.97 5.5 v temperature range -20 85 c v sim output voltage 0 < i load < 30 ma, 3v < v ddsim < 5.5v 2.77 2.8 2.83 v i out output current 30 ma v drop min supply for sim_vcc > 1.75v i load = 50 ma 2.85 v transient line regulation t r = t f = 5 s, v ddsim from 3v to 5.5v, i load = 30 ma 30 mv transient load regulation t r = t f = 5 s, v in = 2.97v, i load from 3 to 27 ma 30 mv i cc quiescent current v ddsim = 5.5v 50 a i cc powerdown current v ddsim = 5.5v 1 a t r rise time i load = 30 ma 10% - 90% v out 500 s i sc limitation current 3v < v ddsim < 5.5v 50 ma v n output noise bw: 10 hz to 100 khz including bandgap noise 1 mvrms
90 at73c203 2742b?pmgmt?03/04 usim digital interface the sim interface conforms to the etsi technical specification etsi ts 102 221 v4.2.0 (2001-04) based on the iso/iec 7816 standard. both t = 0 and t = 1 protocols are supported. the terminal is configured and controlled via several registers: control register (sim_cr) channel status register (sim_csr) buffer status register (sim_bsr) miscellaneous status register (sim_msr) interrupt mask register 1 (sim_imr1) interrupt mask register 2 (sim_imr2) receiver time out register (sim_rtor) baud divisor register (sim_bdr) receiver holding register (sim_rhr) transmitter holding register (sim_thr) transmitter time guard register (sim_ttgr) number errors register (sim_ner) clock divider register (sim_cdr) activation register (sim_ar) all these registers are detailed in table 4, ?at73c203 user interface,? on page 22. figure 25 shows the major blocks required in the interface. figure 25. usim interface digital architecture control logic control/status registers psu generation spi sim_reset sim_vcc receiver interrupt control sim_int transmitter sys_clock clock generation baud_rate_clock sim_io sim_clk
91 at73c203 2742b?pmgmt?03/04 operating conditions clock the clock applied to the sim card is generated by the terminal from the system clock sys_clock (see ?sim clock generation? on page 92). the clock signal can be enabled or disabled by register clken. voltage both class b and c are supported (etsi 102.221 section 5.2, 5.3). they correspond to 3v and 1.8v nominal voltage, respectively. the operating class is selected by register vsel. the first operating condition applied to the card by the terminal should be class c (1.8v). if the card does not provide an answer-to-reset (atr), class b (3v) should be applied to the card (etsi 102.221 section 6.2). this should be managed by software. presence the presence of card status is written in the register pres. an interrupt is generated if the bit pres is changing. this interrupt can be masked in the interrupt mask register. this interrupt is reset with the rstpres bit in control regis- ter sim_cr. initial communication establishment procedures reset the reset register sreset is directly connected to output pin sim_reset. cold reset and activation in order to activate the sim card, electrical circuits should be activated in the following order: 1. sim card voltage should be chosen with vsel (sim_mr). 2. sim clock should be started by writing 1 to clken (sim_cr). 3. i/o line should be activated by setting active in control register sim_cr. 4. after a minimum of 400 sim_clock cycles, the application should rise sreset. the application should be able to detect an absence of atr after 40000 sim_clock cycles. this can be done by using the timer with an initial value of 108 (108 x 372 = 40176 where 372 is the default baud rate divisor). warm reset a warm reset is done by writing to register sreset (sim_cr). the application has to respect a minimum of 400 sim_clock cycles between falling and rising edges of the pin sim_reset. as for a cold reset, the absence of atr should be managed by the application. clken 0 1 sim clock disabled enabled vsel 00 01 10 11 selected voltage disabled disabled 1.8v 2.8v pres 0 1 presence of the sim card not present present
92 at73c203 2742b?pmgmt?03/04 clock stop a clock stop can be done by writing 0 on the register clken. the application should ensure that no activity occurs 1860 sim_clock cycles before the clock is stopped. this is done by using the time-out counter. deactivation in order to deactivate the sim card, electric al circuits should be deactivated in the fol- lowing order: 1. write 0 to sreset. 2. sim clock should be stopped by writing 0 to clken. 3. i/o line should be deactivated by resetting active in control register sim_cr. 4. sim card voltage should be disabled with register vsel. answer to reset (atr) after reset, the terminal expects a default bit rate = 1/372 f, where f is the sim clock fre- quency. this value can be changed afterwards (see below). the initial waiting time (see specification iso 7816-3 section 6.3.2) should be pro- grammed in the timer by the application. the required value is 9600 etus. the atr must be checked by software. sim clock generation the sim clock is generated through a programmable divider. the division factor can be programmed in 4 bits register sim_cdr. figure 26. usim clock generation cdr[3:0] 0000 0001 to 1111 clock division factor no clock cdr[3:0] / 32 / 31 >1 1 0 0 1 bdr[6] bdr[5:0] sim_clk baud_rate_clock / / cdr[3:0] 0 sys_clock
93 at73c203 2742b?pmgmt?03/04 speed enhancement the baud rate can be programmed in the 7-bit register bdr. the etu is one bit rate clock cycle. the baud rate = f/(div1 x div2) where f is the sim clock frequency. div1 is coded on bdr[6]. div2 is coded on bdr[5:0]. before changing the baud rate division factor, the values supported by the sim card have to be checked by doing a pps operation as defined in iso 7816-3 section 7. extra guardtime an extra guardtime can be programmed when sending characters to the card. the 8-bit register sim_ttgr (see ?transmitter time guard register? on page 41) allows an extra time guard from 0 to 255 etu. transmission protocol the sim interface handles all specific requirements defined in iso7816 t = 0 and t = 1 protocol types. it has also some specific features such as maximum character repetition. two 16-byte fifos are provided in order to free cpu resources, one for reception and one for transmission. two 4-bit pointers in the buffer status register (sim_bsr) indi- cate how many characters are present in the fifos, rxptr for receiver fifo, txptr for transmitter fifo. reception the receiver can be reset by using the rstrx command in sim_cr. this empties the rx fifo and the receiver is waiting for a new valid character. when a complete character is received, it is transferred to the receiver fifo and the rxrdy status bit in sim_csr is set. if the fifo is full, the rxfull status bit in sim_csr is set and if a new character is re ceived, the last character in the fifo is overwritten and the ovre status bit in sim_csr is set. the receiver fifo is accessible through receiver holding register (sim_rhr). in the following, an access to sim_rhr means an access to the receiver fifo. t=0 upon detection of a start bit, the following data byte is shifted in the receiver holding register (sim_rhr) when the shift is completed and the parity is checked. if a parity error is detected, the pare bit is set in sim_csr and a low error signal is sent for one elementary time unit (etu), 10.5 etus after the start bit. this error signal is sent from the receiver to the transmitter but can be inhibited by setting the bit irxnack in the reg- ister sim_mr. 1 bit 6 bits bdr[6] bdr[5:0] bdr[6] 0 1 div1 31 32 bdr[5:0] 0 1 - 63 div2 64 bdr[5:0]
94 at73c203 2742b?pmgmt?03/04 t=1 upon detection of a start bit, the following data byte is shifted in the receiver holding register (sim_rhr) when the shift is completed and the parity is checked. if a parity error is detected, the pare bit is set in status register sim_csr. in this protocol there is only one stop bit. time-out this function allows an idle condition on reception to be detected. the maximum delay for which the terminal should wait for a new character to arrive is programmed in sim_rtor (receiver time-out). when this register is set to 0, no time-out is detected. otherwise, the receiver waits for a first character and then initializes a counter, which is decremented at each bit period and reloaded at each byte reception. when the counter reaches 0, the timeout bit in sim_msr is set. the user can restart the wait for a first character with the stto (start time-out) bit in sim_cr. transmission the transmitter can be reset by using the rsttx command in sim_cr. this will empty the tx fifo and the transmitter will be inactive until a new character has to be sent. the transmitter fifo is accessible through the transmit holding register (sim_thr). when a character is written to sim_thr (transmit holding), it is transferred to the shift register as soon as it is empty. whenever the fifo is not full, the txrdy status bit in sim_csr is set. if the transmit shift register and the transmitter fifo are both empty, the txempty bit in sr is set. if the fifo is full and a new character is written to sim_thr, the last character in the fifo will be overwritten. in protocol t=0, if the sim card sends back a non-acknowledgment signal, the status bit txnack in register sim_csr is set. it can be reset by using the rsttxnack com- mand in sim_cr. time-guard the time-guard function allows the transmitter to insert an idle state on the io line between two characters. the duration of the idle state is programmed in sim_ttgr (transmitter time-guard). when this register is set to zero, no time-guard is generated. otherwise, the transmitter holds a high level on sim_io after each transmitted byte for the number of bit periods programmed in sim_ttgr. timings t = 0 the minimum interval between two consecutive characters is at least 12 etus. if two consecutive characters are sent in opposite directions, the minimum interval of time should be 16 etus. this is automatically managed by the hardware. wwt (work waiting time) overflow can be managed by the 16-bit time-out counter. if 65536 cycles are not enough, the timer can be rearmed by using the retto command in register in sim_cr. t = 1 the minimum interval between the leading edge of the start bits of two consecutive characters is at least 11 etus. the block guard time (22 etus) is automatically managed by hardware. cwt (character waiting time) and bwt (block waiting time) can be managed by the time-out counter as for wwt in protocol t=0.
95 at73c203 2742b?pmgmt?03/04 character repetition for t = 0 protocol t = 0 allows character repetition. reception when irxnack is set and a parity error is detected, an error signal is not sent. the received byte is available in the sim_rhr register and the rxrdy bit is set. if irxnack = 0, the number of character repetitions depends on disable successive non-acknowledgment (dsrxnack) bit and max_iteration bits, both in sim_mr. max_iteration is a 3-bit field configurable with a value between 0 and 7. this implies that a character can be repeated up to eight times. if dsrxnack = 0, an error signal is sent on the i/o line as soon as a parity error occurs in the received character. if dsrxnack = 1, successive parity errors are counted up to the value specified in the max_iteration field. these parity errors generate a error signal on the sim_io line. as soon as this value is reached, no additi onal error signal is sent on the i/o line. the flag iteration is asserted. to reset the iteration (sim_msr) flag, the rsit bit must be set in the control regis- ter (sim_cr). transmission a character repetition can be executed if the max_iteration field in sim_mr is differ- ent from 0. if max_iteration = 0, no repetition is done. if max_iteration is different from zero and no parity error has been detected, no rep- etition is done. if max_iteration is different from zero and a parity error has been detected, the transmitter re-sends the corrupted value. if a parity error is still detected, the corrupted value is sent as many times as the value loaded in the max_iteration field. if the number of repetitions of the corrupted value reaches the value loaded in the max_iteration field, the iteration (sim_msr) flag is set. the transmitter is dis- abled until the iteration flag is reset. if at some stage during the repetition sequence, no error parity is detected, repetition is stopped. to reset the iteration (sim_msr) flag, the rsit command can be used, but in that case the transfer will continue if the fifo is not empty and not all characters would have been correctly sent. that's why it is recommended to reset the transmitter with the rsttx command in the control register (sim_cr). error counter if errors occurred during a transfer, it is possible to obtain the total number of errors by reading the register in sim_ner. this is a read-only register reset by a read action. up to 255 errors can be recorded. interrupts all interrupts can be masked in registers sim_imr1 and sim_imr2 rxrdy a character has been received. an interrupt occurs when status bit rxrdy in sim_csr is set. reset of status bit causes reset of interrupt.
96 at73c203 2742b?pmgmt?03/04 rxfull the receiver fifo is full. an interrupt occurs when status bit rxfull in sim_csr is set. reset of status bit causes reset of interrupt. ovre the last character in the receiver fifo has been overwritten. an interrupt occurs when status bit ovre in sim_csr is set. reset of status bit causes reset of interrupt. pa r e a parity error occurred. an interrupt occurs when status bit pare in sim_csr is set. reset of status bit causes reset of interrupt. txrdy the transmitter fifo has one byte space left. an interrupt occurs when status bit txrdy in sim_csr is set. reset of status bit causes reset of interrupt. txempty all characters have been transmitted. an interrupt occurs when status bit txempty in sim_csr is set. reset of status bit causes reset of interrupt. txnack an error bit has been received. an interrupt occurs when status bit txnack in sim_csr is set. reset of status bit causes reset of interrupt. timeout the timer has expired. an interrupt occurs when status bit timeout in sim_msr is set. reset of status bit causes reset of interrupt. iteration the maximum iteration number has been reached. an interrupt occurs when status bit iteration in sim_msr is set. reset of status bit causes reset of interrupt. pres the sim card has been removed or inserted. an interrupt occurs when status bit pres in sim_msr is changing. rstpres command in register sim_cr causes reset of interrupt. rxhalf the receiver fifo is half full. an interrupt occurs when receiver fifo pointer rxptr goes from 7 to 8. reading sim_bsr causes reset of interrupt. txhalf the transmitter fifo is half full. an interrupt occurs when transmitter fifo pointer txptr goes from 9 to 8. reading sim_bsr causes reset of interrupt.
97 at73c203 2742b?pmgmt?03/04 charger control the at73c203 is able to control the charging of two lithium ion batteries from either a psu or usb supply. charging can occur in two different modes as follows: stand-alone mode. the at73c203 preconditions the battery independently of the application processor (the application processor is not powered up). controlled mode. the application processor controls the charging phases via registers accessed via the spi. figure 27. charger control schematic digital control battery2 t9 c14 t10 c15 battery1 usb psu t11 d5 d4 r6 bat1_ch bat2_ch bat2_ch_on bat1_ch_on batsensem batsensep usb_ch_en usb_ch charger control
98 at73c203 2742b?pmgmt?03/04 charge principles stand-alone mode the stand-alone mode occurs only when the usb is plugged in and there is no battery 2 (or it is flat) and battery 1 is flat and the psu unplugged (see ?state machine descrip- tion? on page 15 and figure 30 on page 101). the at73c203 can then choose to precharge battery 1 if the temperature range is within limits. the stand-alone mode is terminated if the charge timer expires or if the voltage of battery 1 goes above 3.8v. the digital core (via the usb_scr register) can put the at73c203 into a mode in which the digital core is off and battery 1 is charged (25 ma) through the usb up to 4.1v. figure 28. stand-alone mode table 29. charger components schematic reference reference bat1 li-ion battery 4.2v-3.0v. permanently connected to module bat2 li-ion battery 4.2v-3.0v. optional battery c14, c15 10 nfx56 10% ceramic capacitor d4, d5 mbra120lt3 (on semiconductor) r6 200 m ? +/- 2% 50 mw t7 si8401dl t11 si1405dl time time 25 ma current 3.8 v voltage stand-alone mode t < timer for stand-alone mode
99 at73c203 2742b?pmgmt?03/04 controlled mode after the digital reset phase, the applicati on processor can launch a charge phase. by default the charge phase is stopped when the application processor wakes up. the charge control includes three charging phases (preconditioning, fast charge and pulsed charge) during which the application processor must check via the monitoring function that the operating temperature is within allowable limits for battery charging. figure 29. controlled mode preconditioning phase battery 1 and battery 2 can be preconditioned to a predetermined voltage from either the psu or usb source. precondition current is set to 25 ma. to enable the precondition phase, the application processor must use the charger con- trol register. to program the preconditioning voltage thres hold, the application processor must use an interrupt, which can be programmed for battery 1 and battery 2 with the over limit registers included in the monitoring function. a safety timer (cha_str_cr) can be launched during this phase. if the safety timer expires, an interrupt is launched and the pre-conditioning phase is automatically stopped. if the pre-conditioning voltage threshold has been reached, the application pro- cessor should put the charger into the fast charge phase. fast charge phase to enable the fast charge phase, the application processor must use the charger control register. the battery is charged at a constant current that can be adjusted (cha_curr in the cha_mr in register). note that battery 1 and battery 2 can not be in the fast charge phase at the same time. 25 ma current voltage preconditioning phase fast charge current preconditioning voltage t < timer for preconditioning t < timer for fast charge t < timer for pulsed phase fast charge phase pulsed charge phase time time
100 at73c203 2742b?pmgmt?03/04 the fast charge is automatically stopped when the battery voltage reaches the regula- tion voltage. the regulation voltage can be tr immed. by default, the voltage is 4.2v. when this voltage is reached an interrupt is sent to warn the microprocessor. a safety timer (cha_str_cr) can be launched during this phase. pulsed charge phase to enable the pulsed charge phase, the application processor must use the charger control register. note that battery 1 and battery 2 can not be in pulsed charge phase at the same time. the charger control uses a hysteretic al gorithm with minimum on-times and minimum off-times of the external pmos. these minimum on-times and off-times can be pro- grammed via registers cha_tminon and cha_tminoff. the battery voltage is sampled every 0.3 millisecond (typical). if the battery voltage is less than the battery regulation voltage, the external pmos fet either turns on or, if already on, remains on. if the battery voltage is greater than, or equal to, the regulation voltage threshold, the fet either turns off or, if already off, remains off until the next sample. at the beginning of the pulsed charge phase, the current stays on for many consecutive cycles between single off periods. as the battery continues to charge, the percentage of time spent in the ?current-on? mode decreases. at the end of the pulsed phase, the cur- rent stays off for many cycles between single ?on? pulses. this phase is automatically stopped when the duty ratio of ?on? cycles to ?off? cycles falls below a threshold which must be programmed trough register cha_tr. additionally, an interrupt is sent to warn the microprocessor. for safety, a timer (cha_str_cr) can be launched during this phase. if this timer expires, an interrupt is launched and the pulsed charge phase is automati- cally stopped. the ?start-up state machine pulsed charge phase? shown in figure 30 on page 101 presents a summary of the pulsed charge phase. refer also to the ?state machine description? on page 15 for more information on the pulsed charge phase. the parameters (cha_tminon, cha_tminoff and cha_tr) can be trimmed in order to be adapted to the battery. to properly choose the parameters, a test must been done with the real battery. at the end of top-off mode, it is preferable to use a small cur- rent (100 ma). a good default value seems to be 200 ms for cha_tminon and cha_tminoff and a duty cycle threshold of 1/64.
101 at73c203 2742b?pmgmt?03/04 figure 30. start-up state machine pulsed charge phase watchdog for safety, during any phase of the controlled mode a watchdog is launched automati- cally. the application processor must rearm the watchdog via the charger control register, cha_cr, at least every 13 s. if during 13 s (typical time), the watchdog has not been rearmed, the charge is stopped. pulse charge phase selected wait for the end of minimum on-time timer wait for the end of minimum off-time timer 2 1 2 1 3 3 pmos_on pmos_off end_charge duty cycle pmos_on/pmos_off < cha_duty duty cycle pmos_on/pmos_off < cha_duty end of pulsed charge phase pmos off charger minimum off-time timer launched pmos on charger minimum on-time timer launched battery voltage > regulation voltage and minimum on-time timer has expired battery voltage > regulation voltage and minimum on-time timer has expired
102 at73c203 2742b?pmgmt?03/04 charger control electrical specifications table 30. charger control electrical specifications symbol parameter condition min typ max units psu charger voltage 4.90 5.0 5.10 v usb usb voltage 4.62 5.0 5.25 v i precond preconditioning current usb or psu 25 ma i ch charge current cha_curr = 11 500 ma cha_curr = 10 300 ma cha_curr = 01 200 ma cha_curr = 00 100 ma v regth regulation voltage threshold cha_volt_trim =000 4.20 v cha_volt_trim =001 4.170 v cha_volt_trim = 010 4.130 v cha_volt_trim = 011 4.10 v cha_volt_trim = 100 4.23 v cha_volt_trim = 101 4.26 v cha_volt_trim = 110 4.30 v cha_volt_trim = 111 4.07 v hystbat1 input hysteresis 2mv timer for stand alone mode 1 h threshold voltage for stand alone mode 3.8 v t accuracy timing accuracy 25 % i cc current consumption 1ma
103 at73c203 2742b?pmgmt?03/04 power dissipation the internal power dissipation depends on the operating mode of the chip; thus, worst case mode is considered. table 31 gives power dissipation values (estimated). quiescent current the at73c203 has two modes: off and active mode. in off mode, the target is to achieve an off time of three months with a 600 ma fully- charged battery. if the self discharge of the battery (maximum 50 a) is taken into consideration, the maximum current of the at73c203 in this mode must be below 220 a. typical measure on rev c: 70 a. table 31. power dissipation (estimated) block name power dissipation (estimated) in mw power switch 50 digital rails (dc/dc converters) 50 charger 300 sim regulator 120 monitoring function 10 core block + digital 20 total 550
104 at73c203 2742b?pmgmt?03/04 package outline (top view) figure 31. 10 x 10 balls, 0.8mm pitch bga package on 9 x 9mm body size for at73c203 10 9 8 7 6 5 4 3 2 1 avss nen_rail4 syst_clk scan_enable vsw therm2 cref vreffuse maxsupply seldc25 seldc175 nc n shutdown vswin gnda vmes gnd_pio psu_pio nen_rail3 pcmcia vsauv therm1 vbias bat2_pio gapsu nint n asic_rese t _request power_en scan_test_md button_in usb_pio portest bat1_pio gabat2 usb_ch nusim_int button_ou t nc nsen gnd_ch gabat1 usb_ch_en batsensep batsensem idbits1 chg_inhibit test1 test2 idbits2 nc nc bat2_ch bat1_ch_on bat2_ch_on bat1_ch idbits3 sdo vddpsu3 vddpsu2 vddpsu1 sim_io sim_vcc sim_pres vddpsu vboost idbits0 sdi gnddc3 dcsense3 dcsense2 dcsense1 nc nc sim_reset sim_clk sclk dl3 gnddc2 dl2 gnddc1 dl1 dl4 gnddc4 vout4 vout3 gnddig dh3 vout2 dh2 vout1 dh1 dh4 dcsense4 vddpsu4 b a d e f h g j k nboard_reset c nc b oard_re set nasic_reset n proc_res et_out nproc_reset
105 at73c203 2742b?pmgmt?03/04 package specification figure 32. at73c203 package specification
printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its produc ts, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature 2742b?pmgmt?03/04 ? atmel corporation 2004 . all rights reserved. atmel ? and combinations thereof are the registered trademarks of atmel corporation or its subsidiaries, semitec ? is the registered trademark of semitec ? ishizuka electronics corporation. intel ? ,is the registered trademark of intel corporation, gowanda ? is the registered trademark of gowanda el ectronics corporation, on semiconductor ? is the registered trademark of on semiconductor corporation. intel ? xscale ? is the trademark of intel corporation. other terms and product names may be the trademarks of others.

▲Up To Search▲

Price & Availability of AT73C203-EK1

	To Download AT73C203-EK1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .